2012 International Symposium on Electronic System Design (ISED)

19-22 Dec. 2012

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  • [Front cover]

    Publication Year: 2012, Page(s): C4
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  • [Title page i]

    Publication Year: 2012, Page(s): i
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  • [Title page iii]

    Publication Year: 2012, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2012, Page(s): iv
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  • Table of contents

    Publication Year: 2012, Page(s):v - x
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  • Message from General Chairs

    Publication Year: 2012, Page(s): xi
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  • Message from Program Chairs

    Publication Year: 2012, Page(s):xii - xiii
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  • Organizing Committee

    Publication Year: 2012, Page(s):xiv - xv
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  • Program Committee

    Publication Year: 2012, Page(s):xvi - xviii
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  • Keynotes

    Publication Year: 2012, Page(s):xix - xxiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Provides an abstract for each of the keynote presentations and may include a brief professional biography of each View full abstract»

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  • [Invited talks - 2 abstracts]

    Publication Year: 2012, Page(s):xxiv - xxv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Synthesis of Reversible Circuits Using Decision Diagrams

    Publication Year: 2012, Page(s):1 - 5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB) | HTML iconHTML

    Due to its promising applications in domains like quantum computation or low-power design, synthesis of reversible circuits has become an intensely studied topic. However, many synthesis methods are limited by non-scalable function representations like truth tables. As an alternative, synthesis exploiting graph-based representations have been suggested. The underlying structure is a decision diagr... View full abstract»

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  • Cleaning Up: Garbage-Free Reversible Circuits by Design Languages

    Publication Year: 2012, Page(s):6 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    Reversible logic is a computational model that ensure that no values are discarded or duplicated. This gives the connection to Landauer's principle if and only if the underlying circuits are garbage-free. This paper shows how to describe and implement garbage-free reversible logic circuits in an easy and concise way. We use two domain-specific languages that are designed to describe reversible log... View full abstract»

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  • Synthesis of Toffoli Networks: Status and Challenges

    Publication Year: 2012, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (167 KB) | HTML iconHTML

    This paper gives a brief overview of the current trends in reversible logic synthesis. The basic building block for reversible circuits considered here is the multiple-control Toffoli gate. Some approaches to synthesis are reviewed and challenges are explained. Since many practical functions are not reversible, they must be embedded into reversible ones, if they are to be implemented using reversi... View full abstract»

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  • Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries

    Publication Year: 2012, Page(s):17 - 22
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (346 KB) | HTML iconHTML

    This paper reviews recent developments on mapping reversible circuits to libraries of elementary quantum gates. The emphasis is on optimization of both the initial reversible circuit and the resulting quantum circuit. At the quantum level, improved realizations of single mixed-polarity multiple-control Toffoli gates are presented as well as techniques for performing quantum gate optimizations acro... View full abstract»

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  • A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process

    Publication Year: 2012, Page(s):23 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    The design of a 6bit 125MS/s Successive Approximation (SAR) Analog to Digital Converter (ADC) that uses modified switching technique has been presented in this paper. This modified switching technique requires only half the number capacitors and achieves a switching energy reduction of about 91.5% when compared with conventional SAR ADC approach. This scheme also reduces by half the DAC capacitor ... View full abstract»

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  • A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications

    Publication Year: 2012, Page(s):28 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    In this paper the implementation of a low power high speed 4-bit Binary Search ADC (BS-ADC) is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the latch-based conventional comparators. The reported structure of the ADC occupies an active area of 0.0157 mm2 and consumes 127 μW of average power wh... View full abstract»

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  • 0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process

    Publication Year: 2012, Page(s):33 - 37
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (222 KB) | HTML iconHTML

    In this paper a low power continuous-time 4th order low pass Butterworth filter operating at power supply of 0.5 V is presented. A 3-dB bandwidth of 1 MHz using technology node of 0.18 μm is achieved. In order to achieve necessary head-room, the filter uses pseudo-differential bulk-driven transconductor. A master-slave based common mode feedback(CMFB) circuit sets the output comm... View full abstract»

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  • Design Space Exploration and Synthesis of CMOS Low Noise Amplifiers

    Publication Year: 2012, Page(s):38 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (222 KB) | HTML iconHTML

    The present work proposes a simple, accurate, fast and exhaustive search procedure for the synthesis of CMOS LNA circuits. The procedure first involves the use of a circuit simulator (Cadence Spectre) to generate a Look Up Table (LUT) containing the device small signal and DC parameters. Then, for a given set of target performance specifications, this LUT is used along with appropriate analytical ... View full abstract»

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  • FPGA Based Efficient Fast FIR Algorithm for Higher Order Digital FIR Filter

    Publication Year: 2012, Page(s):43 - 47
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (301 KB) | HTML iconHTML

    The scope of the paper is to design a new Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure, which are designed for symmetric coefficients that aim at reducing hardware cost in our design with a constraint that the filter tap must be a multiple of 2. The reduction in area is achieved by replacing the adder by a bulky multiplier. For example, for a 4 parallel 36... View full abstract»

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  • Effect of Finite Gain and Bandwidth of Feed-Forward Compensated OTA on Active-RC Integrators: A Case Study

    Publication Year: 2012, Page(s):48 - 51
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    This paper analyses the effect of finite gain-bandwidth of the operational transconductance amplifiers (OTAs) on active-RC integrators. A feed-forward compensated OTA is taken as the building block of active-RC integrator. A mathematical analysis is carried out on a first order low-pass active-RC filter designed in 180 nm CMOS technology to operate at a supply voltage of 0.5 V. A non-ideality fact... View full abstract»

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  • Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution

    Publication Year: 2012, Page(s):52 - 55
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB) | HTML iconHTML

    A novel design for the implementation of the 2M x 3P x 5Q point Discrete Fourier Transform (DFT) computation for Single Carrier-Frequency Division Multiple Access (SC-FDMA) systems as defined by the Long Term Evolution standard is proposed. The design is based on the Systolic Architecture. The decomposition of the DFT computation into factors of two, three, four an... View full abstract»

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  • SoC Time to Market Improvement through Device Driver Reuse: An Industrial Experience

    Publication Year: 2012, Page(s):56 - 61
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    With growing complexity of semiconductor devices due to increase in the functionality along with reduced time to market requirements, the semiconductor companies strive to deliver zero defect products and the associated software in short development cycles. In reduced product development cycle customers expect a quality device and reliable software like device drivers, protocol stacks and other mi... View full abstract»

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  • Confidence Based Power Aware Testing

    Publication Year: 2012, Page(s):62 - 66
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    In modern deep sub-micron technology, it is very crucial to have quality product with low power test and desired level of fault coverage. In this paper, we address a technique to reduce test length with efficiently managed scan power and higher test quality, targeting to achieve a desired level of fault coverage with all essential (marked) faults being covered as well. This can aid in achieving a ... View full abstract»

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  • A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques

    Publication Year: 2012, Page(s):67 - 71
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    A novel value propagation based equivalence checking method of finite state machines with datapath (FSMDs) is presented here for validation of code motion transformations commonly applied during scheduling phase of high-level synthesis. Unlike many other reported techniques, our method is able to handle code motions across loop bodies. This is accomplished by repeated propagation of the mismatched... View full abstract»

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