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2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Date 12-16 March 2012

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Displaying Results 1 - 25 of 326
  • [Front cover]

    Publication Year: 2012, Page(s): c1
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  • [Title page]

    Publication Year: 2012, Page(s): i
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  • [Copyright notice]

    Publication Year: 2012, Page(s): ii
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  • Table of contents

    Publication Year: 2012, Page(s):iv - xxvi
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  • DATE12 sponsors

    Publication Year: 2012, Page(s): xxvii
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  • DATE Executive Committee

    Publication Year: 2012, Page(s):xxviii - xxix
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  • DATE Sponsor Committee

    Publication Year: 2012, Page(s): xxix
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  • Technical programme topic chairs

    Publication Year: 2012, Page(s): xxx
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  • Technical programme committee

    Publication Year: 2012, Page(s):xxxi - xl
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  • Reviewers

    Publication Year: 2012, Page(s):xl - xlv
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  • Foreword

    Publication Year: 2012, Page(s): xlvi
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  • Best paper awards

    Publication Year: 2012, Page(s): xlvii
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  • Tutorials

    Publication Year: 2012, Page(s):xlviii - liv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (73 KB)

    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • EDAA/ACM SIGDA PhD forum at DATE 2012 in Dresden

    Publication Year: 2012, Page(s):lv - lvi
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  • DATE13 Conference and Exhibition: March 18-22, 2013, Alpexpo, Grenoble, France - Call for Papers

    Publication Year: 2012, Page(s): lvii
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  • The mobile society - chances and challenges for micro- and power electronics

    Publication Year: 2012, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (39 KB)

    Summary form only given. Last July, scientists from the ATLAS and CMS experiments at the Large Hadron Collider (LHC) announced the discovery of a new particle with properties that are consistent with the Higgs Boson. Since then, both experiments have continued to collect and analyze data with the goal of learning more about this particle. This talk will review the reasons for introducing the Higgs... View full abstract»

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  • New foundry models - accelerations in transformations of the semiconductor industry

    Publication Year: 2012, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (59 KB)

    Summary form only given. Moore's Law continues to deliver ever-more transistors on an integrated circuit, but discontinuities in the progress of technology mean that the future isn't simply an extrapolation of the past. For example, design cost and complexity constraints have recently caused the microprocessor industry to switch to multi-core architectures, even though these parallel machines pres... View full abstract»

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  • Automated generation of directed tests for transition coverage in cache coherence protocols

    Publication Year: 2012, Page(s):3 - 8
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    Processors with multiple cores and complex cache coherence protocols are widely employed to improve the overall performance. It is a major challenge to verify the correctness of a cache coherence protocol since the number of reachable states grows exponentially with the number of cores. In this paper, we propose an efficient test generation technique, which can be used to achieve full state and tr... View full abstract»

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  • On ESL verification of memory consistency for system-on-chip multiprocessing

    Publication Year: 2012, Page(s):9 - 14
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1092 KB) | HTML iconHTML

    Chip multiprocessing is key to Mobile and high-end Embedded Computing. It requires sophisticated multilevel hierarchies where private and shared caches coexist. It relies on hardware support to implicitly manage relaxed program order and write atomicity so as to provide well-defined shared-memory semantics (captured by the axioms of a memory consistency model) at the hardware-software interface. T... View full abstract»

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  • Generating instruction streams using abstract CSP

    Publication Year: 2012, Page(s):15 - 20
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (97 KB) | HTML iconHTML

    One of the challenges that processor level stimuli generators are facing is the need to generate stimuli that exercise microarchitectural mechanisms deep inside the verified processor. These scenarios require specific relations between the instructions participating in them. We present a new approach for processor-level scenario generation. The approach is based on creating an abstract constraint ... View full abstract»

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  • A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture

    Publication Year: 2012, Page(s):21 - 26
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting instruction level parallelism vs. thread level parallelism. Based on the characteristics of an application or thread the instruction set architecture (ISA) can be adapted to increase performance or reduce resource/power consumption. To bene... View full abstract»

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  • A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

    Publication Year: 2012, Page(s):27 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously. In addition, the on-chip interconnection fabric is extremely high hardware cost for the distributed trace signals. In this paper, we propose a clustering-based scheme which implements concurrent trace for debuggi... View full abstract»

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  • CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

    Publication Year: 2012, Page(s):33 - 38
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB) | HTML iconHTML

    Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D o... View full abstract»

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  • TagTM - accelerating STMs with hardware tags for fast meta-data access

    Publication Year: 2012, Page(s):39 - 44
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB) | HTML iconHTML

    In this paper we introduce TagTM, a Software Transactional Memory (STM) system augmented with a new hardware mechanism that we call GTags. GTags are new hardware cache coherent tags that are used for fast meta-data access. TagTM uses GTags to reduce the cost associated with accesses to the transactional data and corresponding metadata. For the evaluation of TagTM, we use the STAMP TM benchmark sui... View full abstract»

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  • Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

    Publication Year: 2012, Page(s):45 - 50
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB) | HTML iconHTML

    The recent development of non-volatile memory (NVM), such as spin-torque transfer magnetoresistive RAM (STT-RAM) and phase-change RAM (PRAM), with the advantage of low leakage and high density, provides an energy-efficient alternative to traditional SRAM in cache systems. We propose a novel reconfigurable hybrid cache architecture (RHC), in which NVM is incorporated in the last-level cache togethe... View full abstract»

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