2011 21st International Conference on Field Programmable Logic and Applications

5-7 Sept. 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): C1
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  • [Title page i]

    Publication Year: 2011, Page(s): i
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  • [Title page iii]

    Publication Year: 2011, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - xiii
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  • General Chair message

    Publication Year: 2011, Page(s):xiv - xv
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  • A Note from the Program Chairs

    Publication Year: 2011, Page(s):xvi - xviii
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  • Organizing Committee

    Publication Year: 2011, Page(s): xix
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  • Program Committee

    Publication Year: 2011, Page(s):xx - xxiv
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  • Steering Committee

    Publication Year: 2011, Page(s): xxv
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  • Additional Reviewers

    Publication Year: 2011, Page(s):xxvi - xxvii
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  • Sponsors

    Publication Year: 2011, Page(s): xxviii
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  • Accelerating Image Analysis for Localization Microscopy with FPGAs

    Publication Year: 2011, Page(s):1 - 5
    Cited by:  Papers (8)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (487 KB) | HTML iconHTML

    Localization microscopy enhances the resolution of fluorescence light microscopy by about an order of magnitude. Single fluorescent molecules act as switchable markers. Their detected signals can be fitted with a two-dimensional Gaussian distribution and thus located with sub-pixel resolution. In this paper we propose that these fits can be done by calculating the center of mass instead of an iter... View full abstract»

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  • Unifying Finite Difference Option-Pricing for Hardware Acceleration

    Publication Year: 2011, Page(s):6 - 9
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    Explicit finite difference method is widely used in finance for pricing many kinds of options. Its regular computational pattern makes it an ideal candidate for acceleration using reconfigurable hardware. However, because the corresponding hardware designs must be optimised both for the specific option and for the target platform, it is challenging and time consuming to develop designs efficiently... View full abstract»

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  • Leros: A Tiny Microcontroller for FPGAs

    Publication Year: 2011, Page(s):10 - 14
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (197 KB) | HTML iconHTML

    Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An... View full abstract»

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  • Design of a High Switching Frequency FPGA-Based SPWM Generator for DC/AC Inverters

    Publication Year: 2011, Page(s):15 - 19
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (316 KB) | HTML iconHTML

    The Sinusoidal Pulse Width Modulation (SPWM) principle is widely used in power electronic DC/AC converters (inverters) in energy conversion and motor control applications. The digital SPWM generation unit implementations have dominated over their counterparts based on analog circuits. In this paper, an FPGA-based SPWM generator is presented, which is capable to operate at switching frequencies up ... View full abstract»

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  • A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis

    Publication Year: 2011, Page(s):20 - 23
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (16342 KB) | HTML iconHTML

    Thanks to their inherent regularity and reconfigurability, FPGAs offer an ideal structure to manage process variability. Recent works from the literature have addressed the process characterization problem for FPGAs: proposed approaches rely on process sensors (ring oscillators) and a measurement subsystem implemented into the configurable logic blocks. In this article, we propose for the first ti... View full abstract»

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  • An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors

    Publication Year: 2011, Page(s):24 - 29
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (553 KB) | HTML iconHTML

    As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduction for irregular code compared to a soft core processor. ICERs target the hot-spots of programs, and are seamlessly connected via a shared L1 ... View full abstract»

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  • A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs

    Publication Year: 2011, Page(s):30 - 33
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (479 KB) | HTML iconHTML

    The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moores momentum and fuel the next wave of consumer electronics products. However, the benefits of such an integration technology have not been sufficiently explored yet. In this p... View full abstract»

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  • Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory

    Publication Year: 2011, Page(s):34 - 37
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (465 KB) | HTML iconHTML

    Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array can be reconfigured at nanosecond-order, with more than 100 reconfiguration contexts. In addition to that beneficial feature, since ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particl... View full abstract»

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  • An FPGA Solver for SAT-Encoded Formal Verification Problems

    Publication Year: 2011, Page(s):38 - 43
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (203 KB) | HTML iconHTML

    Formal verification is one of the most important applications of the satisfiability (SAT) problem. WSAT and its variants are one of the best performing stochastic local search algorithms. In this paper, we propose an FPGA solver for SAT-encoded verification problems based on a WSAT algorithm. The size of the verification problems is very large, and most of the data used in the algorithm have to be... View full abstract»

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  • FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities

    Publication Year: 2011, Page(s):44 - 49
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    We present a full-parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. The proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Accumulation) component, a second stage containing a pre-threshold potential updating unit with an error approxima... View full abstract»

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  • Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms

    Publication Year: 2011, Page(s):50 - 57
    Cited by:  Papers (8)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (901 KB) | HTML iconHTML

    In the clinical applications, medical image registrations on the images taken from different times and/or through different modalities are needed in order to have an objective clinical assessment of the patient. Viscous fluid registration is a powerful PDE-based method that can register large deformations in the imaging process. This paper presents our implementation of the fluid registration algo... View full abstract»

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  • Latch-Based Performance Optimization for FPGAs

    Publication Year: 2011, Page(s):58 - 63
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (381 KB) | HTML iconHTML

    We explore using pulsed latches for timing optimization -- a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips to implement latch-based optimizations that do not have the power or area drawbacks associated with other timing optimization approaches, such as cl... View full abstract»

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  • XDL-Based Module Generators for Rapid FPGA Design Implementation

    Publication Year: 2011, Page(s):64 - 69
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (463 KB) | HTML iconHTML

    XDLCoreGen is described, a module generator framework which directly generates placed and routed hard macros in XDL. XDLCoreGen is intended to be used in a rapid prototyping flow such as HM Flow, which achieves short FPGA implementation times by bypassing the conventional Xilinx tool flow and directly assembling designs from pre-built hard macros. The structure of XDLCoreGen is described and its u... View full abstract»

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