20-22 April 2011

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Displaying Results 1 - 25 of 33
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Front matter]

    Publication Year: 2011, Page(s):1 - 3
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  • Message from the Organizing Committee chair

    Publication Year: 2011, Page(s):i - ii
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  • Message from the advisory committee chair

    Publication Year: 2011, Page(s): iii
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  • Message from the Program Committee Chairs

    Publication Year: 2011, Page(s):iv - v
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  • List of the Committees members

    Publication Year: 2011, Page(s):vi - viii
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  • Final program

    Publication Year: 2011, Page(s):ix - xvii
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  • Special session speaker's biography

    Publication Year: 2011, Page(s):xviii - xix
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  • Keynote & invited speaker's biography

    Publication Year: 2011, Page(s):xx - xxvii
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (82 KB)

    Summary form only given. Provides an abstract for each of the keynote presentations and, where available, a brief professional biography of each presenter. View full abstract»

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  • Contents

    Publication Year: 2011, Page(s): xxviii
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  • [Special sessions - breaker pages]

    Publication Year: 2011, Page(s):1 - 4
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  • Session II: Poster short speeches

    Publication Year: 2011, Page(s): 1
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  • Poster preface

    Publication Year: 2011, Page(s):1 - 2
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (135 KB)

    Poster covers the same interest areas as the technical contributions by oral presentation, but differs in manner of presentation. They are presented in a visual format designed to encourage informal interaction between authors and attendees. As a result, successful posters will have strong visual impact combined with careful information design to convey project details. This year, we have twenty p... View full abstract»

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  • Session III: Keynote presentation 3

    Publication Year: 2011, Page(s):1 - 2
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  • Session IV: Reconfigurable processors

    Publication Year: 2011, Page(s): 1
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  • FlexGrip™: A small and high-performance programmable hardware for highly sequential application

    Publication Year: 2011, Page(s):1 - 3
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (67 KB) | HTML iconHTML

    Although the state-of-the-art multi-core/many-core processors with SIMD extension are getting powerful enough for full software implementation of highly data-parallel application, highly sequential application still requires dedicated hardware for accelerating its performance because it lacks data-parallelism. In this paper, we propose a novel programmable hardware called FlexGrip™, which aims at ... View full abstract»

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  • SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

    Publication Year: 2011, Page(s):1 - 3
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (795 KB) | HTML iconHTML

    SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm × 4.2mm 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage ... View full abstract»

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  • Session V: High-performance chip-to-chip interconnect

    Publication Year: 2011, Page(s): 1
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  • An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller

    Publication Year: 2011, Page(s):1 - 3
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (167 KB) | HTML iconHTML

    An 80 Gbps dependable communication SoC with four 4X PCIe Rev.2.0 ports has been developed that acts as a communication link with high transfer capability. By using the PCIe I/F, the SoC can address two computing nodes as peers, breaking the traditional PCIe limit of only linking to a single master processor. The SoC also employs an intelligent ICU that supports an initiate data transfer function ... View full abstract»

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  • COOL interconnect low power interconnection technology for scalable 3D LSI design

    Publication Year: 2011, Page(s):1 - 3
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (527 KB) | HTML iconHTML

    3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra... View full abstract»

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  • Session VI: Keynote presentation 4

    Publication Year: 2011, Page(s):1 - 2
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  • Session VII: Low-power designs

    Publication Year: 2011, Page(s): 1
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  • A low-power sync processor with a floating-point timer and universal edge tracer for 3DTV active shutter glasses

    Publication Year: 2011, Page(s):1 - 3
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (135 KB) | HTML iconHTML

    A low-power sync processor chip for 3DTV shutter glasses has been proposed and implemented. The proposed sync processor adopts a newly designed floating point timer to synchronize without any sync reception and an edge tracer for universal sync-packet detection without running the CPU. The floating-point timer allows the input wireless sensor to be turned off, and the edge tracer enables the CPU t... View full abstract»

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  • Loop-Directed Mothballing: Power-gating execution units using fast analysis of inner loops

    Publication Year: 2011, Page(s):1 - 3
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (70 KB) | HTML iconHTML

    Static power dissipation has been identified as a limiting factor in future microprocessor technologies. This paper presents Loop-Directed Mothballing (LDM) to reduce static power by power-gating execution units. The method accurately predicts the resource requirements and limits performance degradation by focussing on inner loops. In simulation, the energy-delay product (EDP) of the processor is ... View full abstract»

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  • A new match line sensing technique in Content Addressable Memory

    Publication Year: 2011, Page(s):1 - 3
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (146 KB) | HTML iconHTML

    The paper presents a new match line sense amplifier for Content Addressable Memory. It successfully addresses the weaknesses of contemporary designs. Extensive simulation results using a 1 V/65 nm CMOS process from STMicroelectronics have verified that the proposed sense amplifier outperforms other five contemporary designs in terms of energy consumption, area requirement and robustness. This is a... View full abstract»

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