1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

Chemical Mechanical Polishing (CMP), a technology born in IBM Confidential culture, has remained true to its heritage not only because of its significant competitive advantage, but because of the history of its birth in the semiconductor industry. In spite of this heritage, CMP has grown from its invention in 1984, to one of the fastest growing segments of the semiconductor equipment industry. In ... View full abstract»

The semiconductor industry, whose long period of sustained growth is in no small measure due to the optical lithography process, is now on the verge of a dilemma. Optical lithography has arrived at a crossroads, and after many years of steady improvement in device performance, device integration, and cost reduction, the industry is facing a major crisis. In Japan, Europe and the U.S., consortiums ... View full abstract»

In this work a 3.97 /spl mu/m/sup 2/ 6T CMOS SRAM bitcell technology has been developed using a logic based platform incorporating a self-aligned local interconnect and copper metallization. This 0.20 /spl mu/m process technology is suitable for stand-alone SRAM applications as well as embedded applications such as digital signal processors. A stable bitcell operation has been demonstrated for pow... View full abstract»

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed and a very low 1.5 V non-WL (word line)-boosting read and sector-erase operations are successfully achieved. Moveover, this cell technology not only maintains the advantages of the P-channel DINOR (DIvided bit line NOR) flash memory, but also realizes the amplification of cell current, which is favorable for fast ac... View full abstract»

The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology ... View full abstract»

A sub-0.25 /spl mu/m technology in manufacturing that is targeted for high-performance CMOS applications is discussed. Aggressive groundrule scaling including SRAM cell size down to 5.4 /spl mu/m/sup 2/ is combined with multiple threshold voltage devices and the first technology in the industry to offer copper interconnects. These features result in minimum unloaded inverter delay of 12.7 ps and e... View full abstract»

This report describes the development and integration of a blanket CVD copper film into advanced microprocessor devices. The in situ deposition of sputtered Tantalum based or CVD Titanium based barrier layers and PVD Cu under and overlayers has been demonstrated to improve film adhesion and device electrical performance. View full abstract»

This paper presents results evaluating the impact of copper (Cu) wiring on a production 64 Mb/0.35 /spl mu/m trench capacitor DRAM technology. There has been considerable progress integrating Cu wiring into high performance logic processes, but little work has been done assessing the viability of Cu integration into a DRAM process. This is an important area of study as performance levels of DRAM t... View full abstract»

This paper reports the drift of Cu ions in various low-permittivity polymer dielectrics to identify Cu barrier requirements for future ULSI integration. Bias-temperature stressing was conducted on Cu-insulator-semiconductor capacitors to investigate Cu+ penetration into the polymers. Our study shows that Cu/sup +/ ions drift readily into poly(arylene ether) and fluorinated polyimide, but much more... View full abstract»

Copper and a low dielectric constant (low-/spl kappa/) material have been successfully integrated in a dual damascene interconnect architecture. The low-/spl kappa/ material (/spl kappa/=2.2) was used as intra-level dielectric and inter-level dielectric, which has led to significant reduction in both intra-level and inter-level capacitance. In addition, low Cu wiring resistance and low Cu via resi... View full abstract»

This paper presents the accelerated inverse narrow channel effect of DRAM cell transistors caused by lateral E-field penetration from drain/source junctions of neighboring cell transistors. This phenomenon strongly increases the threshold voltage fluctuation of cell transistors depending on the junction biases of neighboring cell transistors and will impose physical size and the voltage scaling co... View full abstract»

Recently, electron beam (EB) direct writing has been put to practical use in advanced device fabrication, using for example, a cell projection (CP) method, a variably continuous moving stage, a high current density EB, and high speed deflector amplifier, all of which increase the writing throughput of the EB direct writing system. However, for EB direct writing to be used for advanced DRAMs, the f... View full abstract»

A 0.21 /spl mu/m/sup 2/ 7/sup F/2 trench capacitor DRAM cell with a locally-open globally-folded dual bitline has been fabricated using a 175 nm groundrule. This cell features a trench capacitor, a self-aligned trench-to-diffusion buried strap in direct proximity to the array transistor, shallow-trench device isolation (STI), a self-aligned poly-plug bitline contact, and two-levels of bitline wiri... View full abstract»

A novel structure and fabrication process for a DRAM cell for 4 Gbit and beyond is proposed. A poly-Si pillar transistor is formed on top of a trench capacitor with the top of the pillar transistor being directly connected to the bit line. In order to reduce the process steps, word line formation by a spacer etch and self-aligned bit line contact using CMP process are developed. XTEM micrographs s... View full abstract»

The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 /spl mu/m generations. We show crosstalk to be very impor... View full abstract»

The stochastic net length distribution for global interconnects in a non-homogeneous system-on-a-chip is derived using novel models for netlist information, placement information and routing information. Through comparison with actual product data, it is shown that the new stochastic models successfully predict the global net length distribution of a heterogeneous system. View full abstract»

A novel multi-level interconnect process, realizing air gap structures composed of not new low k materials but conventional SiO/sub 2/ films, has been developed in order to drastically decrease the capacitance between lines. The effective relative dielectric constant of 1.8 is obtained. This process can solve the significant issues associated with air gap structure, such as the via failures due to... View full abstract»

This paper describes excellent Al filling characteristics and low resistance dual damascene interconnects obtained with a new Al reflow process using Nb liner. This novel process can fill vias of AR4 and can achieve 40-50% drop in resistance compared with current RIE-Al lines and reflow-Al lines with Ti liner. These properties are attributed to a slower reaction rate between Nb and Al. Excellent v... View full abstract»

A poly-Si/Al/sub 23//poly-Si capacitor is developed for the simple integration of 256 Mb DRAM and beyond. The oxide equivalent thickness (T/sub oxeq/) was achieved as small as 28 /spl Aring/, which corresponds to the capacitance of 26.8 fF/cell in 256 Mb DRAM with 0.26 /spl mu/m feature size. One of the distinguished characteristics of Al/sub 2/O/sub 3/ capacitor is that the capacitance was even e... View full abstract»

High dielectric constant SrTiO/sub 3/ films (/spl epsiv/=237 or C=70 fF//spl mu/m/sup 2/ measured at 100 kHz) have been fabricated and the dynamic stressing characteristics of these dielectrics has been studied for the first time. Time-dependent dielectric breakdown (TDDB) of SrTiO/sub 3/ is shown to be strongly dependent on frequency and duty cycle under dynamic stressing. On the other hand, diel... View full abstract»

A new, low temperature SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) MOCVD process exhibiting excellent run-to-run repeatability has been developed for high density FeRAM applications. 90% step coverage and good adhesion were achieved on feature sizes down to 0.5 μm on both Pt or SiO/sub 2/ surfaces. Postanneal process optimization resulted in an increase of remanent polarization of about 30%. Electrical cha... View full abstract»

A thorough electrical characterization of BST with focus on lifetime, large device relevant areas (2/sub c/m/sup 2/) and defect density was carried out. As a result we think that BST with an SiO/sub 2/ equivalent thickness t/sub oxeq/ of 5 Å is able to meet the requirements of Gb DRAMs with ±1 V operating voltage. View full abstract»

A high performance embedded SRAM technology for 0.13 μm logic LSIs has been developed. The memory cell size is 2.49 μm/sup 2/ which is the smallest of the 6Tr full-CMOS SRAMs. The concept of this technology is to provide perfect process compatibility with logic parts. This process includes Co salicide and gate/source/drain co-doping and excludes self-aligned contact and local-interconnect. A hole ... View full abstract»