# IEEE Electron Device Letters

## Issue 2 • Feb. 2019

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## Filter Results

Displaying Results 1 - 25 of 61
• ### Front cover

Publication Year: 2019, Page(s): C1
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• ### IEEE Electron Device Letters

Publication Year: 2019, Page(s): C2
| PDF (110 KB)
• ### Table of contents

Publication Year: 2019, Page(s):157 - 159
| PDF (220 KB)
• ### Changes to the Editorial Board

Publication Year: 2019, Page(s): 160
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• ### Changes to the Editorial Board

Publication Year: 2019, Page(s): 161
| PDF (124 KB) | HTML
• ### Changes to the Editorial Board

Publication Year: 2019, Page(s): 162
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• ### Design of a Gate Diode Triggered SCR for Dual-Direction High-Voltage ESD Protection

Publication Year: 2019, Page(s):163 - 166
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A novel gate diode triggered silicon-controlled rectifier (GDTSCR) with dual-direction high-voltage (HV) electrostatic discharge (ESD) protection and a low snap-back voltage is proposed and investigated. Compared to conventional MOS triggered SCR (MTSCR), the GDTSCR has two gate diodes and one additional n-p-n. Superior to the MTSCR, the GDTSCR exhibits a high holding voltage of 15 V, a small trig... View full abstract»

• ### Low-Temperature Fabrication of High Quality Gate Insulator in Metal–Oxide–Semiconductor Capacitor Using Laser Annealing

Publication Year: 2019, Page(s):167 - 170
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This letter reports the fabrication of a high quality gate oxide for metal–oxide–semiconductor field-effect transistors using a continuous-wave blue laser. A thin Zr metal layer was inserted between the dielectric and substrate to increase laser absorption and reduce the interface layer. A simulation of laser irradiation showed that the metal layer insertion induces a significant increase in tempe... View full abstract»

• ### Pulse-Train Method to Measure Transient Response of Field-Effect Transistors

Publication Year: 2019, Page(s):171 - 173
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A simple method to measure the short time-domain output current of field-effect transistors (FETs) is demonstrated. By applying short gate pulses and measuring average output current, the response to very short pulses can be measured and compared with DC measurements. Applied to several novel III–V FETs, the technique shows clearly that when charge trapping and interface states affect drain curren... View full abstract»

• ### Demonstration of HfO2-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer

Publication Year: 2019, Page(s):174 - 176
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HfO2-based gate stacks with titanium (Ti) incorporated into a GeOx interfacial layer (IL) were fabricated on p-Ge substrates. X-ray photoelectron spectroscopy results, incorporating Ti, can efficiently suppress the GeO volatilization. This contributed to achievement of an equivalent oxide thickness of approximately 0.8 nm, a low interface states density View full abstract»

• ### Deep p-Ring Trench Termination: An Innovative and Cost-Effective Way to Reduce Silicon Area

Publication Year: 2019, Page(s):177 - 180
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A new type of high-voltage termination, namely the “deep p-ring trench” termination design for high-voltage, high-power devices, is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required but also removes the need for an additional mask as is the case of the tra... View full abstract»

• ### Improved Electrical Characteristics of Bulk FinFETs With SiGe Super-Lattice-Like Buried Channel

Publication Year: 2019, Page(s):181 - 184
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Although SiGe super-lattice (SL) buried channel was proposed to enhance carrier mobility in MOSFETs, its application on FinFETs is not reported yet. The electrical characteristics of nFinFETs with SiGe and SiGe SL-like buried channels were studied in this letter for the first time. The results show that the electron mobility of nFinFETs with SiGe buried channel is enhanced by an SL-like structure.... View full abstract»

• ### Normally-Off AlGaN/GaN Heterojunction Metal-Insulator-Semiconductor Field-Effect Transistors With Gate-First Process

Publication Year: 2019, Page(s):185 - 188
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In this letter, AlGaN/GaN heterojunction metal–insulator-semiconductor field-effect transistors with gate-first process were developed for normally-off operation with p-GaN cap layers and SiNx dielectrics. To avoid the effect of the annealing process on the gate, a low-temperature ohmic contact technique was developed at an annealing temperature of about 500 °C for 20 min in N2 View full abstract»

• ### Raman Thermography of Peak Channel Temperature in $\beta$ -Ga2O3 MOSFETs

Publication Year: 2019, Page(s):189 - 192
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$\beta$ -Ga2O3 is an attractive material for high-voltage applications and has the potential for monolithically integrated RF devices. A combination of Raman nano-particle thermometry measurement and thermal simulation has been used to measure the peak channel temperature due to self-heating in View full abstract»

• ### Solution-Processed Physically Transient Resistive Memory Based on Magnesium Oxide

Publication Year: 2019, Page(s):193 - 195
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In this letter, physically transient resistive memory devices based on solution-processed MgO films were demonstrated for the first time. Stable and reproducible resistive switching memory performances were achieved with Mg/solution-processed MgO/W devices, which have larger OFF/ON resistance ratio ( $10^{5}$ ) than the Mg/sput... View full abstract»

• ### Electro-Thermal Erasing at 104-Fold Faster Speeds in Charge-Trap Flash Memory

Publication Year: 2019, Page(s):196 - 199
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An erasing method capable of speeds 104-fold faster compared with those by the conventional Fowler–Nordheim (FN) erasing technique is experimentally demonstrated in a gate-all-around junctionless (JL) charge-trap flash memory device using thermal excitation with the aid of electric field. A gate electrode serving as a built-in heater generates Joule heat for thermal excitation of trappe... View full abstract»

• ### Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation

Publication Year: 2019, Page(s):200 - 203
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In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfi... View full abstract»

• ### Investigation of Threshold Voltage Distribution Temperature Dependence in 3D NAND Flash

Publication Year: 2019, Page(s):204 - 207
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The impact of temperature on array Vth distribution was investigated in 3D NAND flash. Cell Vth distributions were obtained under different program and read temperature splits. After the page is programmed under high temperature, it is found that the high tail of Vth distribution exhibits a larger shift than the low tail, during read at different temperatures (85 °C and −25 °C). On the contrary, t... View full abstract»

• ### An Offset Readout Current Sensing Scheme for One-Resistor RRAM-Based Cross-Point Array

Publication Year: 2019, Page(s):208 - 211
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The uneven sneak-path currents in resistive random access memory (RRAM) severely constrain the array size. To overcome this issue, we propose an innovative readout scheme that can fully offset the sneak-path currents in one-resistor (1R) RRAM array. Furthermore, the bit cell resistance $({R}_{\text {cell}}{)}$ in an RRAM arra... View full abstract»

• ### Suppression of Self-Heating Effects in 3-D V-NAND Flash Memory Using a Plugged Pillar-Shaped Heat Sink

Publication Year: 2019, Page(s):212 - 215
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Self-heating effects (SHEs) in 3-D V-NAND flash memory are investigated using simulations. First, temperature increase is estimated during the read operation, and a hot spot region along the bit-line is identified. Then, a novel bilayered macaroni filler is proposed to relieve the SHEs. A highly thermally conductive layer is plugged into the macaroni oxide filler as a heat sink. The heat dissipati... View full abstract»

• ### Recovery of Cycling Endurance Failure in Ferroelectric FETs by Self-Heating

Publication Year: 2019, Page(s):216 - 219
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This letter investigates the impact of self-heating on the post-cycling functionality of a scaled hafnium oxide-based ferroelectric field-effect transistor (FeFET). The full recovery of FeFET switching properties and data retention after the cycling endurance failure is reported. This is achieved by damage annealing through localized heating, which is intentionally induced by a large current flow ... View full abstract»

• ### Efficient Dipole Coupled Nanomagnetic Logic in Stress Induced Elliptical Nanomagnet Array

Publication Year: 2019, Page(s):220 - 223
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This letter presents an efficient dipole coupled nanomagnetic logic scheme clocked by voltage-induced stress. The logic signals can be transmitted to an array of eight elliptical nanomagnets in one cycle. Transmission speed is increased 1–2 times versus the conventional stress scheme while the required stress is reduced. Micromagnetic simulations illustrate that both increasing the tilt angleof th... View full abstract»

• ### Flexible Low-Voltage IGZO Thin-Film Transistors With Polymer Electret Gate Dielectrics on Paper Substrates

Publication Year: 2019, Page(s):224 - 227
| | PDF (720 KB) | HTML

Polymer electret shows a good electrostatic polarization effect, resulting in very high-density charge accumulation in semiconducting channel layer at low gate voltage. In this letter, graphene oxide enhanced poly(vinyl alcohol) film was used as the gate dielectric for flexible low-voltage indium-gallium-zinc-oxide thin-film transistors (TFTs) on paper substrates. High performance with a high curr... View full abstract»

• ### Inkjet-Printed Self-Aligned Short-Channel Metal-Oxide Thin-Film Transistors Based on Coffee Stripe Dewetting Method

Publication Year: 2019, Page(s):228 - 231
| | PDF (776 KB) | HTML

It is difficult to implement high-resolution layer-to-layer alignment by direct inkjet printing because of the limitation of position accuracy of the common inkjet printer. The poor alignment of conventional printers generally causes large parasitic overlap capacitances between the gate and source/drain (S/D) of thin-film transistors (TFTs), which degrades device operating speeds. In this paper, a... View full abstract»

• ### Anomalous Positive Bias Stress Instability in MoS2 Transistors With High-Hydrogen-Concentration SiO2 Gate Dielectrics

Publication Year: 2019, Page(s):232 - 235
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For the first time, in this letter, the anomalous positive bias stress instability of the back gated monolayer polycrystal molybdenum disulfide (MoS2) field-effect transistors with high-hydrogen-concentration SiO2 gate dielectrics is reported. It is found that the threshold voltage shifts exhibit a pronounced turnaround behavior from a positive shift to a negative shift when ... View full abstract»

## Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Jesus A. del Alamo

alamo@mit.edu