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Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Date 8-12 March 2010

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Displaying Results 1 - 25 of 363
  • [Front cover]

    Publication Year: 2010 , Page(s): c1
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  • [Title page]

    Publication Year: 2010 , Page(s): 1
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  • [Copyright notice]

    Publication Year: 2010 , Page(s): i
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  • Table of contents

    Publication Year: 2010 , Page(s): ii - xxviii
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  • Date executive Committee

    Publication Year: 2010 , Page(s): xxix - xxx
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  • Technical programme topic chairs

    Publication Year: 2010 , Page(s): xxxi
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  • Technical Program Committee

    Publication Year: 2010 , Page(s): xxxii - xxxviii
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  • list-reviewer

    Publication Year: 2010 , Page(s): xxxix - xlii
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  • Foreword

    Publication Year: 2010 , Page(s): xliii
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  • Best Paper awards

    Publication Year: 2010 , Page(s): xliv
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  • Tutorials [9 abstracts]

    Publication Year: 2010 , Page(s): xlv - xlviii
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (108 KB)  

    Presents abstracts of tutorials from the conference proceedings. View full abstract»

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  • 2010 EDAA / ACM SIGDA PhD Forum at DATE in Dresden

    Publication Year: 2010 , Page(s): l - li
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  • Call for papers

    Publication Year: 2010 , Page(s): lii
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  • All things are connected

    Publication Year: 2010 , Page(s): 1
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (68 KB)  

    Summary form only given. Design of complex system is essentially about connections: Connection of concepts, connection of objects, connection of teams. And products of the future will be connected seamlessly across physical and virtual domains. Connections can produce systems that offer more than the sum of the components but they can also yield to systems that are less powerful than the sum of th... View full abstract»

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  • Wireless communication - successful differentiation on standard technology by innovation

    Publication Year: 2010 , Page(s): 2
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (73 KB)  

    Summary form only given. The rise of the wireless Internet is the megatrend in communication industry. Mobile communication devices will be the dominant platform for information access, gaming, music and spending time with distant friends. About 5 bn or three quarters of the world population is using mobile phones. Internet enabled mobile phones at affordable cost will be the most common Internet ... View full abstract»

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  • Loosely Time-Triggered Architectures for Cyber-Physical Systems

    Publication Year: 2010 , Page(s): 3 - 8
    Cited by:  Papers (5)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (686 KB)  

    Cyber-Physical Systems require distributed architectures to support safety critical real-time control. Kopetz' Time-Triggered Architectures (TTA) have been proposed as both an architecture and a comprehensive paradigm for systems architecture, for such systems. To relax the strict requirements on synchronization imposed by TTA, Loosely Time-Triggered Architectures (LTTA) have been recently propose... View full abstract»

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  • Energy-efficient real-time task scheduling with temperature-dependent leakage

    Publication Year: 2010 , Page(s): 9 - 14
    Cited by:  Papers (13)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (169 KB)  

    Leakage power consumption contributes significantly to the overall power dissipation for systems that are manufactured in advanced deep sub-micron technology. Different from many previous results, this paper explores leakage-aware energy-efficient scheduling if leakage power consumption depends on temperature. We propose a pattern-based approach which divides a given time horizon into several time... View full abstract»

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  • Predicting energy and performance overhead of Real-Time Operating Systems

    Publication Year: 2010 , Page(s): 15 - 20
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (748 KB)  

    We present a high-level method for rapidly and accurately estimating energy and performance overhead of Real-Time Operating Systems. Unlike most other approaches, which rely on Transaction-Level Modeling (TLM), we infer the information we need directly from executing the algorithmic specification, without needing to build any high-level architectural model. We distinguish two main components in ou... View full abstract»

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  • Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling

    Publication Year: 2010 , Page(s): 21 - 26
    Cited by:  Papers (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (296 KB)  

    With new technologies, temperature has become a major issue to be considered at system level design. In this paper we propose a temperature aware idle time distribution technique for energy optimization with dynamic voltage scaling (DVS). A temperature analysis approach is also proposed which is accurate and, yet, sufficiently fast to be used inside the optimization loop for idle time distribution... View full abstract»

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  • Multicore soft error rate stabilization using adaptive dual modular redundancy

    Publication Year: 2010 , Page(s): 27 - 32
    Cited by:  Papers (8)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (274 KB)  

    The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can be an increased processor exposure to soft errors. To address this issue, a flexible fault prevention mechanism has been developed to selectively enable a small amount of per-core dual modular redundancy (DMR) in response to... View full abstract»

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  • A fully-asynchronous low-power framework for GALS NoC integration

    Publication Year: 2010 , Page(s): 33 - 38
    Cited by:  Papers (26)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (257 KB)  

    Requiring more bandwidth at reasonable power consumption, new communication infrastructures must provide adequate solutions to guarantee performance during physical integration. In this paper, we propose the design of a low-power asynchronous Network-on-Chip which is implemented in a bottom-up approach using optimized hard-macros. This architecture is fully testable and a new design flow is propos... View full abstract»

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  • Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller

    Publication Year: 2010 , Page(s): 39 - 44
    Cited by:  Papers (6)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1504 KB)  

    Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We propose a microcoded controller as a hardware module in each node to connect the core, the local memory and the network. The controller is programmable where the DSM functions such as virtual-to-physical address translation, memory ... View full abstract»

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  • MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture

    Publication Year: 2010 , Page(s): 45 - 50
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (101 KB)  

    The shared-memory model has been adopted, both for data exchange as well as synchronization using semaphores in almost every on-chip multiprocessor implementation, ranging from general purpose chip multiprocessors (CMPs) to domain specific multi-core graphics processing units (GPUs). Low-latency synchronization is desirable but is hard to achieve in practice due to the memory hierarchy. On the con... View full abstract»

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  • AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs

    Publication Year: 2010 , Page(s): 51 - 56
    Cited by:  Papers (6)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (230 KB)  

    Aggressive technology scaling has an ever-increasing adverse impact on the lifetime reliability of microprocessors. This paper proposes a novel simulation framework for evaluating the lifetime reliability of processor-based system-on-a-chips (SoCs), namely AgeSim, which facilitates designers to make design decisions that affect SoCs' mean time to failure. Unlike existing work, AgeSim can simulate ... View full abstract»

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  • Statistical SRAM analysis for yield enhancement

    Publication Year: 2010 , Page(s): 57 - 62
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (544 KB)  

    This paper presents an automated technique to perform SRAM wide statistical analysis in presence of process variability. The technique is implemented in a prototype tool and is demonstrated on several 45 and 32nm industry-grade SRAM vehicles. Selected case studies show how this approach successfully captures non-trivial statistical interactions between the cells and the periphery, which remain unc... View full abstract»

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