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Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on

Date July 29 2009-Aug. 1 2009

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  • [Front cover]

    Publication Year: 2009 , Page(s): C1
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  • [Title page i]

    Publication Year: 2009 , Page(s): i
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  • [Title page iii]

    Publication Year: 2009 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009 , Page(s): iv
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  • Table of contents

    Publication Year: 2009 , Page(s): v - x
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  • Preface

    Publication Year: 2009 , Page(s): xi
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  • Conference organizers

    Publication Year: 2009 , Page(s): xii
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  • Program Committee / Reviewers

    Publication Year: 2009 , Page(s): xiii
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  • Keynotes

    Publication Year: 2009 , Page(s): xiv - xvii
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    Summary form only given. The Jet Propulsion Laboratory, California Institute of Technology, is NASA's lead center for robotic exploration of the solar system. Scientific investigation of Mars has been of primary importance, with success of the Phoenix Lander, ongoing operation of the Mars Exploration Rovers, and construction of the 2011 Mars Science Laboratory rover. Additionally, technology development for steep terrain access and sample acquisition with return is also being prepared for the next decade. But Mars is not the only focus of our efforts - prototypes are under development for mobile habitats on the Moon, as well as aerial exploration of Titan and Venus. This talk will provide an overview of the technology development and mission infusion pathways for these challenging scenarios, and provide some recent results from our Mars exploration experience. View full abstract»

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  • A Multi-cellular Developmental Representation for Evolution of Adaptive Spiking Neural Microcircuits in an FPGA

    Publication Year: 2009 , Page(s): 3 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    It has been shown that evolutionary and developmental processes can be used for emergence of scalability, robustness and fault-tolerance in hardware. However, designing a suitable representation for such processes is far from straightforward. Here, a bio-inspired developmental genotype-phenotype mapping for evolution of spiking neural microcircuits in an FPGA is introduced, based on a digital neuron model and cortex structure suggested and verified previously by the authors. The new developmental process is based on complex multi-cellular protein-protein and gene-protein interactions and signaling. Suitability of the representation for evolution of useful architectures and its adaptability is shown through statistical analysis and examples of scalability, modularity and fault-tolerance. View full abstract»

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  • EvoCaches: Application-specific Adaptation of Cache Mappings

    Publication Year: 2009 , Page(s): 11 - 18
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. View full abstract»

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  • Intermediate Level FPGA Reconfiguration for an Online EHW Pattern Recognition System

    Publication Year: 2009 , Page(s): 19 - 26
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    We propose a field programmable gate array (FPGA) implementation for a run-time adaptable evolvable hardware classifier system. Previous implementations have been based on a high-level virtual reconfigurable circuit technique which requires many FPGA resources. We therefore apply an intermediate level reconfiguration technique which consists of using the FPGA lookup tables as shift registers for reconfiguration purposes. This leads to significant resource savings, reducing the classifier circuit size to less than one third of the original implementation. This in turn has made it possible to implement a larger, more accurate classifier than before, giving 97.5% recognition accuracy for a face image application. Experiments also show that a reduction of data element resolution can lead to further resource savings while still maintaining high classification accuracy. View full abstract»

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  • Evolution of Impulse Bursts Noise Filters

    Publication Year: 2009 , Page(s): 27 - 34
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    The paper deals with evolutionary design of impulse burst noise filters. As proposed filters utilize the filtering window of 5times5 pixels, the design method has to be able to manage 25 eight-bit inputs. The large number of inputs results in an evolutionary algorithm not able to produce reasonably working filters because of the so-called scalability problem of evolutionary circuit design. However, the filters are designed using an extended version of Cartesian Genetic Programming which enables to reduce the number of inputs by selecting the most important of them. Experimental evaluation of the method has shown that evolved filters exhibit better results than conventional solutions based on various median filters. View full abstract»

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  • Adapting a Genotype-phenotype Mapping to Phenotypic Complexity

    Publication Year: 2009 , Page(s): 35 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (195 KB) |  | HTML iconHTML  

    The marvel of biological development has motivated researchers to apply artificial development in bio-inspired systems. Among the possible features of artificial development that are being investigated is the potential for improving scalability of evolutionary optimization techniques,by applying artificial development as an indirect mapping.Currently, few guidelines exist as to when development is likely to achieve such improvements. We investigate one guideline based on the complexity of the phenotypic objective and propose a grammatical mapping which can adapt to this complexity. Earlier findings on the correlation between the performance of indirect mappings and phenotypic complexity are confirmed in a new context. Adaptation of an indirect mapping to phenotypic complexity is shown to work well given certain conditions. View full abstract»

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  • Polymorphic FIR Filters with Backup Mode Enabling Power Savings

    Publication Year: 2009 , Page(s): 43 - 50
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (431 KB) |  | HTML iconHTML  

    A polymorphic FIR filter is proposed which can operate in two modes. The first mode is considered as a standard mode in which the filter performs a normal operation. In the second mode, the filter operates with reduced power supply voltage (Vdd), some filter coefficients are reconfigured (as response to the change of the polymorphic gates function which is controlled by Vdd) and some parts of the filter are disconnected. Experimental results indicate that while power consumption can significantly be reduced when half of the taps is suspended the filter is still able to achieve a reasonable quality of filtering. View full abstract»

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  • A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA

    Publication Year: 2009 , Page(s): 51 - 56
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (413 KB) |  | HTML iconHTML  

    A flexible bit-stream level evolvable hardware (EHW) platform is proposed in order to efficiently utilize the programmable logic resources of FPGA when evolving digital circuits. This platform is based on the FuDan FPGA device. An adaptive variable-size look-up-table (LUT) array structure is proposed with the optimal Genetic Algorithm to evolvable circuits. The experiment results showed that the proposed platform is more flexible, and it not only can make good use of FPGA logic resources, but also has a quick evolving speed. View full abstract»

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  • Location-Aware, Flexible Task Management for Collaborating Unmanned Autonomous Vehicles

    Publication Year: 2009 , Page(s): 59 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    Unmanned autonomous vehicles (UAVs) are emerging as a breakthrough concept in technology. A main challenge related to UAV control is devising flexible strategies with predictable performance in hard-to-predict conditions. This paper proposes an approach to performance predictive collaborative control of UAVs operating in environments with fixed targets. The paper offers detailed experimental insight on the quality, scalability and computational complexity of the proposed method. View full abstract»

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  • Evolvable Hardware Based Gray-level Image Enhancement

    Publication Year: 2009 , Page(s): 67 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1958 KB) |  | HTML iconHTML  

    A simple image enhancement technique based upon evolvable hardware is presented. Improving visual appearance is achieved by evolved histogram stretching transformation (evolved circuit). The performance is compared with the classical histogram equalization method using traditional measures of enhancement. Experimental results will be presented to show that the proposed technique offers better performance than the classical histogram equalization method. View full abstract»

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  • On-Board Vision Processing for Small UAVs: Time to Rethink Strategy

    Publication Year: 2009 , Page(s): 75 - 81
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (833 KB) |  | HTML iconHTML  

    The ultimate research goal for unmanned aerial vehicles (UAVs) is to facilitate autonomy of operation. Research in the last decade has highlighted the potential of vision sensing in this regard. Although vital for accomplishment of missions assigned to any type of unmanned aerial vehicles, vision sensing is more critical for small aerial vehicles due to lack of high precision inertial sensors. In addition, uncertainty of GPS signal in indoor and urban environments calls for more reliance on vision sensing for such small vehicles. With off-line processing does not offer an attractive option in terms of autonomy, these vehicles have been challenging platforms to implement vision processing on-board due to their strict payload capacity and power budget. The strict constraints drive the need for new vision processing architectures for small unmanned aerial vehicles. Recent research has shown encouraging results with FPGA based hardware architectures. This paper reviews the bottle necks involved in implementing vision processing on-board,advocates the potential of hardware based solutions to tackle strict constraints of small unmanned aerial vehicles and finally analyzes feasibility of ASICs, Structured ASICs and FPGAs for use on future systems. View full abstract»

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  • Integrating Feature Values for Key Generation in an ICmetric System

    Publication Year: 2009 , Page(s): 82 - 88
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    This paper investigates the practicalities of combining values derived from measurable features of given integrated electronic circuits in order to derive a robust encryption key, a technique termed ICmetrics. Specifically the paper explores options for the precise techniques required to combine the derived feature values in order to ensure key stability. Key stability is an essential component of any encryption system but this must be combined with a guarantee of key diversity between devices. View full abstract»

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  • Dynamically Adapted Low-Energy Fault Tolerant Processors

    Publication Year: 2009 , Page(s): 91 - 97
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    The constant advances on scaling have introduced several issues to the design of processing structures in new technologies. The closer one gets to nano-scale devices, the more necessary are methods to develop circuits that are able to tolerate high defect densities. At the same time, beyond area costs, there is a pressure to maintain energy and power dissipation at acceptable levels, which practically forbids classical redundancy. This paper presents a dynamic solution to provide reliability and reduce energy of a microprocessor using a dynamically adaptive reconfigurable fabric. The approach combines the binary translation mechanism with the sleep transistor technique to ensure graceful degradation for software applications, while at the same time can reduce energy by shutting off the power supply of the unused and the defective resources of a reconfigurable fabric. View full abstract»

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  • Partial Bitstream 2-D Core Relocation for Reconfigurable Architectures

    Publication Year: 2009 , Page(s): 98 - 105
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (531 KB) |  | HTML iconHTML  

    Field programmable gate arrays (FPGAs) potentially offer enhanced reliability, recovery from failures through partial and dynamic reconfigurations, and eliminate the need for redundant hardware typically used in fault-tolerant systems. Our earlier work on scalable self-configurable architectures for reusable space systems (SCARS) describes a partial reconfiguration based self-healing architecture. The implementation of this architecture with the currently available industry tools has taught us a few valuable lessons. Generating the partially reconfigurable cores has acute restrictions that limit our ability to relocate the cores to other regions of the FPGA leading to poor area utilization. State of the art relocation approaches in the academia employ complex relocation management mechanisms which prohibit these solutions to operate at run time. In this paper, we propose a methodology for run-time 2-D core relocation to overcome the above issues. We show that our approach increases reconfiguration area utilization by 36% and reduces partial bitstream storage memory usage by 91% when compared to our base implementation. Conventional solutions restrict a given functionality to be partially reconfigured in a predetermined area. This technology enables the designer to move any core to anywhere on the FPGA fabric providing more resource availability when recovering from failure. View full abstract»

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  • Defect Tolerance of an Optically Reconfigurable Gate Array with a One-time Writable Volume Holographic Memory

    Publication Year: 2009 , Page(s): 106 - 111
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB) |  | HTML iconHTML  

    Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the ORGAs capability of perfectly parallel programmability enables avoidance of those defective areas through alternative use of other non-defective areas. Moreover, a holographic memory to store contexts is known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory.Consequently, damage of a holographic memory rarely affects its diffraction pattern or a reconfiguration context. For that reason, ORGAs are extremely robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability.This paper presents experimentation related to the defect tolerance of new optically reconfigurable gate array with a one-time easily writable volume holographic memory. View full abstract»

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  • Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate

    Publication Year: 2009 , Page(s): 112 - 119
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    In programmable logic devices, the timing requirements change depending on what datapath is being mapped and the level of pipelining required. The added flexibility of such architectures translates to complexity in the design of their clocking scheme, both on the silicon and software level. Using asynchronous techniques to design the programmable elements and interconnects simplifies this problem by replacing the global clock signal with local handshaking. In asynchronous programmable devices, the handshaking protocol implements communication and synchronisation among the components of any mapped datapath irrespective of its length. This paper describes the design of an asynchronous substrate for implementing highly pipelined datapaths. A novel technique for conditional acknowledge synchronisation was used in the interconnect design. Two asynchronous arrays of coarse-grain adders and multipliers were built and compared with an equivalent clocked architecture. For a sample FFT, our asynchronous designs showed a reduction of up to 10% in energy consumption and 4.5% in area, which came at a cost of a 2.5% reduction in throughput over the equivalent synchronous implementation. View full abstract»

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  • A Sixteen-Context Dynamic Optically Reconfigurable Gate Array

    Publication Year: 2009 , Page(s): 120 - 125
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    Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on a programmable device. Such dynamic reconfiguration necessitates two important features: fast reconfiguration and numerous contexts. However, because fast reconfiguration and numerous contexts share a tradeoff relation on current VLSIs, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma.ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DORGAs)that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a 16-context DORGA architecture. Furthermore, we present experimental results: 530-833 ns reconfiguration times and 5-9.375 us retention times. View full abstract»

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