2009 International Conference on Field Programmable Logic and Applications

31 Aug.-2 Sept. 2009

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  • [Front and back covers]

    Publication Year: 2009, Page(s):c1 - c4
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  • [Title page]

    Publication Year: 2009, Page(s):i - ii
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  • Preface

    Publication Year: 2009, Page(s):iii - iv
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  • Organizing Committee

    Publication Year: 2009, Page(s):v - vi
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  • Program Committee

    Publication Year: 2009, Page(s):vii - xii
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  • Steering Committee

    Publication Year: 2009, Page(s):xiii - xiv
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  • Additional reviewers

    Publication Year: 2009, Page(s):xv - xviii
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  • Table of contents

    Publication Year: 2009, Page(s):xix - xxxii
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  • Customizable domain-specific computing

    Publication Year: 2009, Page(s): 1
    Cited by:  Papers (1)
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  • In search of agile hardware

    Publication Year: 2009, Page(s): 2
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  • The evolution of architecture exploration of programmable devices

    Publication Year: 2009, Page(s): 3
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  • FPGA challenges and opportunities at 40nm and beyond

    Publication Year: 2009, Page(s): 4
    Cited by:  Papers (2)
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  • Virtex-6 and Spartan-6, plus a look into the future

    Publication Year: 2009, Page(s): 5
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  • MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

    Publication Year: 2009, Page(s):6 - 11
    Cited by:  Papers (18)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1343 KB) | HTML iconHTML

    MuCCRA-cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90 nm CMOS process consisting of four dies each of which has a 4 times 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and... View full abstract»

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  • Hardware implementation of MPI_Barrier on an FPGA cluster

    Publication Year: 2009, Page(s):12 - 17
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    Message-Passing is the dominant programming model for distributed memory parallel computers and Message-Passing Interface (MPI) is the standard. Along with point-to-point send and receive message primitives, MPI includes a set of collective communication operations that are used to synchronize and coordinate groups of tasks. The MPI_Barrier, one of the most important collective procedures, has bee... View full abstract»

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  • Fast critical sections via thread scheduling for FPGA-based multithreaded processors

    Publication Year: 2009, Page(s):18 - 25
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (619 KB) | HTML iconHTML

    As FPGA based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these systems. Previous work has demonstrated that support for multithreading in soft processors can tolerate pipeline and I/O latencies as well as improve overall system throughput-however earlier work assumes an abundance of ... View full abstract»

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  • A biophysically accurate floating point somatic neuroprocessor

    Publication Year: 2009, Page(s):26 - 31
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    Biophysically accurate neuron models have emerged as a very useful tool for neuroscience research. These models are based on solving differential equations that govern membrane potentials and spike generation. The level of detail that needs to be presented in the model to accurately emulate the behaviour of an organic cell is still an open question, although the timing of the spikes is considered ... View full abstract»

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  • CNP: An FPGA-based processor for Convolutional Networks

    Publication Year: 2009, Page(s):32 - 37
    Cited by:  Papers (109)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1107 KB) | HTML iconHTML

    Convolutional networks (ConvNets) are biologically inspired hierarchical architectures that can be trained to perform a variety of detection, recognition and segmentation tasks. ConvNets have a feed-forward architecture consisting of multiple linear convolution filters interspersed with pointwise non-linear squashing functions. This paper presents an efficient implementation of ConvNets on a low-e... View full abstract»

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  • Noise impact of single-event upsets on an FPGA-based digital filter

    Publication Year: 2009, Page(s):38 - 43
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (957 KB) | HTML iconHTML

    Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in... View full abstract»

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  • Compiler assisted runtime task scheduling on a reconfigurable computer

    Publication Year: 2009, Page(s):44 - 50
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (740 KB) | HTML iconHTML

    Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems is the scheduling and allocation of the tasks on the reconfigurable fabric. In this paper we present a two level scheduling mechanism for tightly coupled reconfigurable architecture machines. To overcome the complexity o... View full abstract»

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  • Data parallel FPGA workloads: Software versus hardware

    Publication Year: 2009, Page(s):51 - 58
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (603 KB) | HTML iconHTML

    Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) with manual hardware design. Recent research has demonstrated that soft processors augmented with support for vector instructions provide significant improvements in performance and scalability for data parallel workloads... View full abstract»

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  • Generating high-performance custom floating-point pipelines

    Publication Year: 2009, Page(s):59 - 64
    Cited by:  Papers (22)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (564 KB) | HTML iconHTML

    Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators are costly to design, and application designers tend to rely on less efficient off-the-shelf operators. To address this issue, an open-source architecture generator framework is introduced. Its salient features are an eas... View full abstract»

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  • Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

    Publication Year: 2009, Page(s):65 - 72
    Cited by:  Papers (11)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (620 KB) | HTML iconHTML

    Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations whe... View full abstract»

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  • Exploring reconfigurable architectures for explicit finite difference option pricing models

    Publication Year: 2009, Page(s):73 - 78
    Cited by:  Papers (13)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (608 KB) | HTML iconHTML

    This paper explores the application of reconfigurable hardware and graphics processing units (GPUs) to the acceleration of financial computation using the finite difference (FD) method. A parallel pipelined architecture has been developed to support concurrent valuation of independent options with high pricing throughput. Our FPGA implementation running at 106 MHz on an xc4vlx160 device demonstrat... View full abstract»

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  • Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming

    Publication Year: 2009, Page(s):79 - 85
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (703 KB) | HTML iconHTML

    As a step torward a viable, single-issue out-of-order soft core, this work presents copy-free checkpointing (CFC), an FPGA-friendly register renaming design. CFC supports speculative execution by implementing checkpoint recovery. Compared against the best conventional register renaming implementation CFC requires 7.5x to 6.4x fewer LUTs and is at least 10% faster. View full abstract»

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