2009 Symposium on VLSI Technology

The modes of interaction within a system are important in understanding many artificial and natural entities. It sounds like a cliche to point out the importance of seeing the brain as a system. Even so, today we do not understand the essential systems level features that make it possible for the brain to realize its remarkable functionality, including dynamical adaptability, sensori-motor coordin... View full abstract»

For the past 40 years, the scaling of CMOS device technology has enabled system performance to double every two years. However, emerging classes of applications for which network-speed processing and data-intensive modeling are integral components will demand a much faster rate of improvement, such as 2x/year in order to reach exaflop capabilities (100x-1000x over present systems) by the end of th... View full abstract»

A novel 3-D NAND flash memory device, VSAT (Vertical-Stacked-Array-Transistor), has successfully been achieved. The VSAT was realized through a cost-effective and straightforward process called PIPE (planarized-Integration-on-the-same-plane). The VSAT combined with PIPE forms a unique 3-D vertical integration method that may be exploited for ultra-high-density Flash memory chip and solid-state-dri... View full abstract»

Vertical Gate NAND (VG-NAND) Flash array with multi-active layers has been successfully integrated for the first time. VG-NAND confirmed stable operations of program, body erase, and read. There is no aggravation on program disturbance with increased number of layers due to an architecture of VG-NAND with vertical blocks. View full abstract»

20 nm-node planer MONOS NAND Flash memory is developed for the first time. Excellent performances such as fast program speed are realized without using FinFET structure. Furthermore, potential of tight Vth distribution is confirmed using 50 nm-node cells. These properties indicate that planer MONOS cell technology developed in this work can be one of candidates for multi-level NAND Flash memory wi... View full abstract»

Vertical NAND flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalabili... View full abstract»

Recent LSI technologies require the introduction of a wide variety of materials and structures in addition to conventional aggressive down-scaling. As a result, present semiconductor devices contain various kinds of nano-scale interfaces and nano-structures. In this paper, we show that conventional physics concepts cannot be applied directly to these interfaces or structures and that construction ... View full abstract»

Advanced gate dielectric stacks are comprised of multiple layers of different materials, including high-k gate dielectrics, high-mobility semiconductor channels, metal gate electrodes and interfacial layers with sub-nanometer thickness. The composition, point defect chemistry, interface atomic structure and interaction between the layers determine the properties of novel gate stacks. This paper re... View full abstract»

Charged defects in the gate insulating oxide cause various degradations in operating MOSFET such as flat-band voltage shifts or threshold voltage instabilities. Excess or deficient oxygen atoms in the oxide layer are relevant to those fixed charges, and thus oxygen concentration must be carefully controlled in the fabrication process. Given the fact that the optimum ambient atmosphere strongly dep... View full abstract»

Electron-holography electrostatic-potential analysis, in conjunction with transmission-electron-microscopy crystal-defect analysis, revealed how halo-implantation and millisecond annealing (MSA) conditions affect defect distributions at source/drain junctions in scaled MOSFETs. The key findings of this analysis are as follows: first, nanometer-scale defects exist at the junction near the gate, sec... View full abstract»

This paper presents a real-time observation on microstructure evolution under electrical programming pulses directly on phase-change memory cells developed with 90-nm technology for the first time. The feasibility of this in-situ TEM experiment was successfully confirmed through the observed memory-switching behavior, and it was found that slow quenching crystallization enhanced the grain growth r... View full abstract»

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: Vt < plusmn 0.45 V (at Lg = 60 nm) at EOT les 1.4 nm, with 105 times Jg reduction compared to SiO2. This scheme integrates several simplifications and improvements for the ... View full abstract»

For the first time, we present good yielding 64 Mb SRAM test-chip with the smallest cell using dual/triple gate oxide process flow in 28 nm node. The low power technology platform continues scaling trend and extends SiON/poly technology beyond 32 nm node with gate density of 2.3times higher than that of 45 nm, and integrates high density (0.127 um2) and low Vccmin (0.155 um2)... View full abstract»

A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain and extensions are effectively doped by an implant-free process to successfully reduce series resistance below 200 Omegaldrm. A zero-silicon-loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabl... View full abstract»