2009 International Symposium on Code Generation and Optimization

22-25 March 2009

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  • [Front cover]

    Publication Year: 2009, Page(s): C1
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  • [Title page i]

    Publication Year: 2009, Page(s): i
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  • [Title page ii]

    Publication Year: 2009, Page(s): ii
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  • [Title page iii]

    Publication Year: 2009, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - vii
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  • Message from General Co-chairs

    Publication Year: 2009, Page(s): viii
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  • Message from the Program Chair

    Publication Year: 2009, Page(s): ix
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  • Organizing Committee

    Publication Year: 2009, Page(s): x
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  • Program Committee

    Publication Year: 2009, Page(s): xi
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  • Additional reviewers

    Publication Year: 2009, Page(s): xii
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  • Sponsors

    Publication Year: 2009, Page(s): xiii
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  • Fourth Workshop on Software Tools for MultiCore Systems (STMCS 2009)

    Publication Year: 2009, Page(s): xiv
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  • Open64 Workshop

    Publication Year: 2009, Page(s): xv
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  • Seventh Workshop on Optimizations for DSP and Embedded Systems (ODES 2009)

    Publication Year: 2009, Page(s): xvi
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  • Exploiting Parallelism Using GPUs and Other Hardware-Assisted Methods (EPHAM 2009)

    Publication Year: 2009, Page(s): xvii
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  • Workshop on Infrastructures for Software/Hardware Co-design (WISH 2009)

    Publication Year: 2009, Page(s): xviii
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  • Tutorial on SSA-Based Register Allocation

    Publication Year: 2009, Page(s): xix
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    Provides an abstract of the tutorial presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • IntelĀ© Threading Building Blocks: Programming for Current and Future Multicore Platforms

    Publication Year: 2009, Page(s): xx
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  • Tutorial on Software Transactional Memory

    Publication Year: 2009, Page(s): xxi
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (27 KB)

    Provides an abstract of the tutorial presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • An Evolution of General Purpose Processing: Reconfigurable Logic Computing

    Publication Year: 2009, Page(s): xxii
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  • The Next Generation of Compilers

    Publication Year: 2009, Page(s): xxiii
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  • Communication-Sensitive Static Dataflow for Parallel Message Passing Applications

    Publication Year: 2009, Page(s):1 - 12
    Cited by:  Papers (25)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (419 KB) | HTML iconHTML

    Message passing is a very popular style of parallel programming, used in a wide variety of applications and supported by many APIs, such as BSD sockets, MPI and PVM. Its importance has motivated significant amounts of research on optimization and debugging techniques for such applications. Although this work has produced impressive results, it has also failed to fulfill its full potential. The rea... View full abstract»

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  • Reducing Memory Ordering Overheads in Software Transactional Memory

    Publication Year: 2009, Page(s):13 - 24
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (447 KB) | HTML iconHTML

    Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total Store Ordering (TSO). To execute these algorithms correctly on processors with relaxed memory models, explicit fence instructions may be required on every transactional access, and neither the processor nor the compiler may b... View full abstract»

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  • Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs

    Publication Year: 2009, Page(s):25 - 34
    Cited by:  Papers (8)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug. To avoid such violations, programmers need to provide explicit synchronizations or insert fence instructions. In this paper, we propose a scheme to detect and eliminate potential SC ... View full abstract»

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