[1990] Proceedings of the International Conference on Application Specific Array Processors

5-7 Sept. 1990

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  • Proceedings of the International Conference on Application Specific Array Processors (Cat. No.90CH2920-7)

    Publication Year: 1990
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    Freely Available from IEEE
  • The RAP: a ring array processor for layered network calculations

    Publication Year: 1990, Page(s):296 - 308
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors have designed and implemented a ring array processor, RAP, for fast implementation of layered neural network algorithms. The RAP is a multi-DSP system targeted at continuous speech recognition using connectionist algorithms. Four boards, each with four Texas Instruments, TMS 320C30 DSPs, serve as an array processor for a 68020-based host running a real-time operating system. The overal... View full abstract»

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  • PASIC. A sensor/processor array for computer vision

    Publication Year: 1990, Page(s):352 - 366
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The PASIC prototype chip contains 256×256 photosensors, a linear array of 256 A/D converters, two 256 8-bit shift registers, 256 bit-serial processors, and a 256×256 bit dynamic RAM. It appears to be a viable architecture for low-level vision processing. The processors operate in SIMD model at 20 MHz. To avoid high speed transfer of analog data, an A/D converter in the form of a linear... View full abstract»

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  • GRAPE: a special-purpose computer for N-body problems

    Publication Year: 1990, Page(s):180 - 189
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    GRAPE (GRAvity PipE) is a special-purpose computer designed to accelerate the numerical integration of the astrophysical N-body problem. The prototype hardware, GRAPE-1, is designed as the backend processor that calculates the gravitational interaction between particles. All other calculations are performed on the host computer connected to GRAPE-1. For large-N calculations (... View full abstract»

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  • Array processing on finite polynomial rings

    Publication Year: 1990, Page(s):284 - 295
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The disadvantage of computations using finite rings is the need to compute over many different rings in order to produce useful dynamic ranges of computation. By mapping integers into polynomial rings, one can replace the different rings by the replication of the same ring with considerable computational advantages. The authors present the methodology of such a mapping strategy, and discuss the ap... View full abstract»

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  • Digit-serial DSP architectures

    Publication Year: 1990, Page(s):341 - 351
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The authors present a systematic unfolding transformation technique to transform bit-serial architectures into equivalent digit-serial ones. The novel feature of the technique is the generation of functionally correct control circuits in the digit-serial architectures. Bit-serial systems process one bit of a word or sample in a clock cycle. For some applications bit-serial architectures may be too... View full abstract»

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  • Design of run-time fault-tolerant arrays of self-checking processing elements

    Publication Year: 1990, Page(s):168 - 179
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A design method for array architectures from regular dependence graphs (DGs) is extended for the design of reconfigurable arrays. The original design method is combined to a single step mapping of the DG with arbitrary dimension n onto the final signal flow graph (SFG) with dimension k. This eliminates the need for recursive application of a mapping which reduces the dimension of... View full abstract»

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  • A practical runtime test method for parallel lattice-gas automata

    Publication Year: 1990, Page(s):782 - 793
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    The authors describe a test method for lattice-gas automata of the type introduced by U. Frisch et al. (1986). The test method consists of inserting test patterns into the initial state of the automaton and using a graphics display to detect errors. The test patterns are carefully constructed limit cycles that are disrupted by errors occurring at any level of the simulator system. The patterns can... View full abstract»

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  • Implementation of systolic algorithms using pipelined functional units

    Publication Year: 1990, Page(s):272 - 283
    Cited by:  Papers (1)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    The authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of initiating a new operation before the previous one has been completed. The method permits transformation of a SA so that it can be efficiently executed using PFUs. The method is based ... View full abstract»

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  • Channel complexity analysis for reconfigurable VLSI/WSI processor arrays

    Publication Year: 1990, Page(s):329 - 340
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The authors propose a general method to analyze channel complexity for a 2D array with a given domain constraint. A domain-based reconfiguration scheme can be divided into two phases: assignment and interconnection. In the assignment phase a logical cell is assigned to a fault-free cell under a domain constraint by assignment rules. In the interconnection phase connections between the assigned log... View full abstract»

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  • An improved multilayer neural model and array processor implementation

    Publication Year: 1990, Page(s):389 - 400
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    The authors present a method for obtaining faster learning in a multilayer neural network. The key ingredient is the concept of floating positive/negative thresholds used in the output neurons to interpret the output states. In a traditional multilayer perceptron, the output state is 1 or 0, depending on whether the activation value exceeds the fixed target threshold or not. The proposed approach ... View full abstract»

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  • Designing specific systolic arrays with the API15C chip

    Publication Year: 1990, Page(s):505 - 517
    Cited by:  Papers (3)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The API15C processor, a building block for different systolic structures, is designed exclusively for single-instruction-multiple data (SIMD) execution mode. To support this mode, the instruction set includes special control instructions. Three parallel I/O ports are available for different interconnection schemes. The API15C chip is designed in a CMOS 2-μm technology. It contains 45000 transis... View full abstract»

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  • Scheduling affine parameterized recurrences by means of

    Publication Year: 1990, Page(s):100 - 110
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The authors present new scheduling techniques for systems of affine recurrence equations. They show that it is possible to extend earlier results on affine scheduling to the case when each variable of the system is scheduled independently of the others by an affine timing-function. This new technique makes it possible to analyze systems of recurrence equations with variables in different index spa... View full abstract»

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  • Extensions to linear mapping for regular arrays with complex processing elements

    Publication Year: 1990, Page(s):156 - 167
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The optimal architectural design of the processing elements (PEs) for an application specific regular array (RA) is nontrivial if the application has a complex operation set. The authors present an approach that extends the conventional, linear time-space transformation for such cases. In application-specific-integrated-circuit (ASIC) architectures, one has the freedom to fine-tune all aspects of ... View full abstract»

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  • A systolic array for nonlinear adaptive filtering and pattern recognition

    Publication Year: 1990, Page(s):700 - 711
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A systolic array for multidimensional fitting and interpolation using (nonlinear) radial basis functions (RBFs) is proposed. The fit may be constrained very simply to ensure that the resulting surface takes a pre-determined value at one or more specific points. The RBF processor is capable of performing a wide range of complex pattern recognition tasks. The processor, which constitutes a form of n... View full abstract»

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  • Bit-level systolic algorithm for the symmetric eigenvalue problem

    Publication Year: 1990, Page(s):770 - 781
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    An arithmetic algorithm is presented which speeds up the parallel Jacobi method for the eigen-decomposition of real symmetric matrices. After analyzing the elementary mathematical operations in the Jacobi method (i.e. the evaluation and application of Jacobi rotations), the author devises arithmetic algorithms that effect these mathematical operations with few primitive operations (i.e. few shifts... View full abstract»

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  • Algorithmic mapping of neural network models onto parallel SIMD machines

    Publication Year: 1990, Page(s):259 - 271
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    The authors consider parallel implementation of neural network computations of fine grain SIMD machines. The authors show a mapping of a neural network having n nodes and e connections onto a parallel machine having (n+e) PEs arranged in an array of √n+e×√n+e PEs such that routing for each update iteration of... View full abstract»

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  • CMOS VLSI Lukasiewicz logic arrays

    Publication Year: 1990, Page(s):469 - 480
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Lukasiewicz logic arrays (LLAs) are massively parallel analog computers organized as binary trees of identical processing elements. The authors have designed and performed preliminary tests on a series of CMOS VLSI LLAs whose cells perform Lukasiewicz implication (→). The authors describe the LLA architecture and its relationship to cellular automata, describe the CMOS VLSI implementation of ... View full abstract»

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  • Systolic architectures for decoding Reed-Solomon codes

    Publication Year: 1990, Page(s):67 - 77
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A systolic implementation of a Reed-Solomon decoder is presented which with minor modification is suitable for BCH and Goppa codes. The various operations involved in decoding such codes were analyzed and the results are described. Systolic array architectures are derived for the various steps including the syndrome calculation, key equation solution and error evaluation. Since the throughput of t... View full abstract»

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  • A fault-tolerant two-dimensional sorting network

    Publication Year: 1990, Page(s):317 - 328
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The authors evaluate a class of sorting algorithms which can be adapted to a faulty network with nearest neighbor interconnections by determining a suitable indexing scheme. A worst case sorting time of O(N) is proved for these sorters. Simulation results show that the average sorting time of the fault-tolerant sorters is only slightly higher than O(√N), a... View full abstract»

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  • Systolic two-port adaptor for high performance wave digital filtering

    Publication Year: 1990, Page(s):379 - 388
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The authors present a VLSI circuit for implementing wave digital filter (WDF) two-port adaptors. Considerable speedups over conventional designs have been obtained using fine grained pipelining. This has been achieved through the use of most significant bit (MSB) first carry-save arithmetic, which allows systems to be designed in which latency L is small and independent of either coeffic... View full abstract»

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  • Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor

    Publication Year: 1990, Page(s):202 - 213
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    The authors present the concept of vector register windows (VRWs) geared towards large scale matrix computation and image processing applications. The VRWs consist of multiple windows for vector registers providing parallel access and manipulation of large matrix data in the orthogonal multiprocessor (OMP). The number of windows and the number of registers in a window are dynamically reconfigurabl... View full abstract»

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  • Towards the automated design of application specific array processors (ASAPs)

    Publication Year: 1990, Page(s):414 - 425
    Cited by:  Papers (2)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The authors describe the architecture and VLSI design of GLiTCH, an associative processor array chip designed for computer vision applications. The design is built from a library of cells, which can be used in conjunction with high level functional specifications to rapidly design new application specific array processors. The objective is to design a system which will allow application specific a... View full abstract»

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  • Byte-serial convolvers

    Publication Year: 1990, Page(s):530 - 541
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    It is shown that previously proposed bit-serial convolver schemes (with weights in parallel form), working with zero separation between samples, can be transformed into byte-serial input schemes with a comparable clock rate, thus affording an increase in sampling rate equal to the number of bits in each byte. This is achieved by adopting a modified carry save circuit. The proposed schemes are base... View full abstract»

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  • Recursive algorithms for AR spectral estimation and their array realizations

    Publication Year: 1990, Page(s):121 - 132
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Autoregressive (AR) spectral estimation is widely used in various fields. However, a trade-off between performance and computational complexity is sometimes faced. Two recursive computing algorithms individually applied to the wide-sense stationary and highly nonstationary environments are presented. These algorithms have good numerical properties, high computing parallelism, and data locality. VL... View full abstract»

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