[1988] Proceedings. International Conference on Systolic Arrays

25-27 May 1988

Filter Results

Displaying Results 1 - 25 of 67
  • Proceedings of the International Conference on Systolic Arrays (Cat. No.88CH2603-9)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • Systolic array for 2-D adaptive beamforming

    Publication Year: 1988, Page(s):1 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (385 KB)

    A pipelined architecture for implementing a 2-D digital adaptive beamformer is described. The architecture relies heavily on a triangular systolic structure as a means of solving recursive least-squares problems based on the QRD algorithm due to J.G. McWhirter (1983). A manifold of triangular systolic arrays, which in the limit takes the form of a cosmic cube, is used. With the proper time skew fo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient systolic array for MVDR beamforming

    Publication Year: 1988, Page(s):11 - 20
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    An efficient systolic array for computing the minimum variance distortionless response (MVDR) from an adaptive antennas array is described. The MVDR beamforming problem amounts to minimizing, in a least-squares sense, the combined output from an antenna array subject of K independent linear equality constraints each of which corresponds to a chosen 'look direction'. The array is fully pipelined an... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of synthetic aperture radar algorithms on a systolic/cellular architecture

    Publication Year: 1988, Page(s):21 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Two sequences of operations necessary for implementation of high-resolution image formation in strip and spotlight modes of the synthetic-aperture radar (SAR) are presented. The sequences are mapped onto a systolic/cellular architecture. The mapping includes parallel implementation of all the basic operations and the pertinent data communication. Detailed estimates of the computation times are pro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient feature extractions by uniform structure threshold logic arrays

    Publication Year: 1988, Page(s):33 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (193 KB)

    Uniform structure threshold logic arrays (USTA) with multi-inputs and multioutputs are proposed for the efficient extraction of important features from time-series multidimensional signals. The fundamental characteristics of an USTA are examined, showing which features can be extracted. The USTA has been used to vertical, horizontal, 45 degrees , and -45 degrees components of characters.<<ET... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architecture of a programmable systolic array

    Publication Year: 1988, Page(s):41 - 49
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB)

    The architecture of a simple but programmable linear systolic array tuned to support a variety of symbolic computations is presented. The system, the Brown Systolic Array (B-SYS) is currently being implemented in CMOS. B-SYS demonstrates that programmable processor arrays may be made fully systolic with no need for local program memory or global instruction broadcasting. Any hazards introduced by ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesizing optimal family of linear systolic arrays for matrix computations

    Publication Year: 1988, Page(s):51 - 60
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (383 KB)

    A method is proposed for designing a family of linear systolic arrays for matrix-oriented problems for which two-dimensional arrays have been designed. The design exhibits a tradeoff between local storage, s, and number of processing elements, n. The arrays are linear, with each processor having storage O(s),1<or=s<or=n, for n*n matrix problems. The input matrices are fed as two-speed data s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Theory for systolizing global computational problems

    Publication Year: 1988, Page(s):61 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A theory is presented for rasterizing a class of two-dimensional problems including signal/image processing, computer vision, and linear algebra. The rasterization theory is steered by an isomorphic relationship between the multidimensional shuffle-exchange network (mDSE) and the multidimensional butterfly network (mDBN). Many important multidimensional signal-processing problems can be solved on ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New architectures for systolic hashing

    Publication Year: 1988, Page(s):73 - 82
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB)

    Two- and three-dimensional systolic architectures are proposed for the hash table data structure (hashing). The parallel systolic hashing architecture provides the facility for implementing the hash operations of Insert, Delete, and Member in a constant time complexity. The importance and advantages of extending sequential hashing to a parallelized form are discussed. An implementation is presente... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linear systolic array for least-squares estimation

    Publication Year: 1988, Page(s):83 - 92
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB)

    The use of square-root-free linear systolic array structure to perform the QR decomposition needed in the solution of least-squares (LS) problems is proposed. A form of the Kalman filter algorithm is applied to perform the recursive LS estimation. Compared with the conventional triangular systolic array structure for LS estimation, the linear array has the advantage of requiring less area and bein... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A cellular algorithm for straight line extraction

    Publication Year: 1988, Page(s):93 - 102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Straight-line-edge extraction can be carried out in two successive phases: identifying the pixels that belong to edges and conducting straight-line segments from these edge pixels. A parallel approach based on a cellular algorithm is proposed for the second phase. Each cell sends a message that compiles distances between a pattern segment and the real segment on the image. The value of the message... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A one dimensional systolic array for solving arbitrarily large least mean square problems

    Publication Year: 1988, Page(s):103 - 112
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (461 KB)

    The design is presented of a one-dimensional systolic array for solving arbitrarily large least-mean-square problems involving QR decomposition and a triangular system of equations. The main characteristics of this array are maximization of array utilization, thus achieving a minimum global computation time, and low complexity of the resulting array, which can also be used in problems such as matr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance evaluation of the HERMES multibit systolic array architecture for low level processing tasks

    Publication Year: 1988, Page(s):113 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The performance of the various parts of the HERMES multiprocessor vision system is evaluated. HERMES is an autonomous, hierarchical, heterogenic vision processing system, consisting of N/sup 2//4/sup i/, 0<or=i<or=log/sub 2/N, processor nodes, where N*N is the size of a picture and i is a resolution parameter. HERMES receives the picture information directly from the environment, using photo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On partitioning the Faddeev algorithm

    Publication Year: 1988, Page(s):125 - 134
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB)

    Partitioned schemes for computing the Faddeev algorithm are derived, using a graph-based methodology. Such implementations are obtained by performing transformations on the fully parallel dependence graph of the algorithm. Linear and two-dimensional structures are derived and evaluated in terms of throughput, I/O bandwidth, utilization of processing elements, and overhead due to partitioning. The ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Systolic arrays for implementation of order-recursive least-squares adaptive filtering algorithms

    Publication Year: 1988, Page(s):135 - 144
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (461 KB)

    Three systolic arrays suitable for implementation of order-recursive least-squares (ORLS) adaptive algorithms are considered. It is shown that they can be constructed using two types of elementary cells. A classification of systolic implementations of the ORLS adaptive algorithms is given by exploiting the possible variations of the elementary cells. The investigation of the array structures and v... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A systolic architecture for the symmetric tridiagonal eigenvalue problem

    Publication Year: 1988, Page(s):145 - 150
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    The first step in the development of a chip set to support eigenvalue-eigenvector-based estimation algorithms is presented. It is based on the assumption that an averaging technique will produce a symmetric covariance matrix. Such a matrix can be reduced to a symmetric tridiagonal matrix, and hence the eigenvalues and eigenvectors can be found by successive iterations involving QR decomposition. T... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Systolic FFT algorithms on Boolean cube networks

    Publication Year: 1988, Page(s):151 - 162
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    A description is given of a systolic Cooley-Tukey fast Fourier transform algorithm for Boolean n-cubes with a substantial amount of storage per cube node. In mapping a Cooley-Tukey type FFT to such a network, the main concerns are effective use of the high connectivity/bandwidth of the Boolean n-cube, the computational resources, the storage bandwidth, if there is a storage hierarchy, and the pipe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel architectures for artificial neural nets

    Publication Year: 1988, Page(s):163 - 174
    Cited by:  Papers (38)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (615 KB)

    The key aspects of the modeling, algorithm, and architecture for artificial neural nets (ANNs) are reviewed. A programmable systolic array meant for a variety of connectivity patterns for ANNs is proposed. Considered in the design are both the search and learning phases of a class of ANNs. A system-theoretic approach is adopted to elucidate modeling issues for ANNs. On the basis the issues of expr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stereo matching of satellite images with transputers

    Publication Year: 1988, Page(s):175 - 182
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (355 KB)

    A demanding problem involving several algorithmic phases with varying degrees of regularity and data dependence is used to show that a network of transputers programmed in OCCAM has all the attributes needed to explore several processing paradigms. Two alternative organizations of the problem on a network of 21 transputers are compared from the standpoints of speed, hardware efficiency, and ease o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The use of linear arrays for image processing

    Publication Year: 1988, Page(s):183 - 192
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB)

    The problem of deciding upon an architecture that is suitable for a broad spectrum of image-processing applications is presently unsolved, at least partly because of the intrinsic difficulty of the processing tasks involved. The author considers the claims of one candidate, the linear array, by examining its generic characteristics and surveying a number of current systems. The author also conside... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A million transistor systolic array graphics engine

    Publication Year: 1988, Page(s):193 - 202
    Cited by:  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (621 KB)

    A description is given of a million transistor systolic array graphics engine (SAGE) that can render a horizontal 3-D span in every clock cycle at the rate of 25 million spans/s, independent of the pixel length of the span. For the average span length in the 10-32 pixel range, this translates into 250-800 million pixels/s. Assuming that the front end of the system can generate a span in every cloc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A systolic array with constant I/O bandwidth for the generalized Fourier transform

    Publication Year: 1988, Page(s):207 - 216
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB)

    A linear systolic array for computing the generalized Fourier transform is proposed. The transform, which is an extension of the discrete Fourier transform, is briefly reviewed. The basic architecture is formally presented and proved, and an example is given. Some implementation issues are addressed. The array is versatile in the sense that it can compute a variety of different transforms. The arr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A massively parallel systolic array processor system

    Publication Year: 1988, Page(s):217 - 225
    Cited by:  Papers (2)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The design of a massively parallel processor, comprised of 2304-bit-serial processor elements arranged in a 48 by 48 systolic array, is described. The system consists of the processor array, a microstore controller, and a host computer interface. Program development tools are available on the host computer. The processor array uses 32 NCR GAPP (Geometric Arithmetic Parallel Processor) microprocess... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of array structured maximum likelihood decoders

    Publication Year: 1988, Page(s):227 - 236
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay commutating switching processors for MLD have been concatenated to construct... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Regular processor arrays for matrix algorithms with pivoting

    Publication Year: 1988, Page(s):237 - 246
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (487 KB)

    It is shown how to obtain regular (though nonsystolic) processor arrays for algorithms with pivoting. First, the fact that pivoting algorithms cannot be systolic is established. Then it is shown how regular iterative algorithms can be formulated for the Gaussian elimination algorithm with partial pivoting and how the algorithm can then be implemented on the so-called regular iterative arrays (loca... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.