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Embedded Systems Letters, IEEE

Issue 1 • Date March 2015

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Displaying Results 1 - 15 of 15
  • Table of contents

    Publication Year: 2015 , Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Publication Year: 2015 , Page(s): C2
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  • Guest Editorial: Special Section on Embedded System Security

    Publication Year: 2015 , Page(s): 1 - 2
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  • Design and Operation of Secure Cyber-Physical Systems

    Publication Year: 2015 , Page(s): 3 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (625 KB) |  | HTML iconHTML  

    This letter proposes a holistic framework for the design and operation of secure and reliable resource-constrained cyber-physical systems. The proposed framework combines control-theoretic methods, information security notions and computational models to characterize tradeoffs among different design and operation objectives. We quantify the intricate relation among control performance, system security and platform schedulability through a minimal set of interface variables. We argue that security mechanisms and control algorithms need to be codesigned and comanaged with the embedded platform, so as to avoid the design of algorithms that are too expensive to implement on the embedded platform, or significantly impede design objectives such as performance and timing robustness. View full abstract»

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  • NoC-Based Protection for SoC Time-Driven Attacks

    Publication Year: 2015 , Page(s): 7 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (647 KB) |  | HTML iconHTML  

    Systems-on-chip (SoCs) based on many core architectures can be attacked. Malicious processes can infer secrets from on-chip sensible traffic by evaluating the degradation on their communication performance. Such a threat rises from the resource sharing. In order to avoid such time-driven attacks, the network-on-chip (NoC) can integrate mechanisms to isolate different communication flows. In this letter, we propose two mechanisms, random arbitration and adaptive routing, that dynamically allocate the SoC resources to avoid such attacks. We compare our approach to the unique previous work under several traffic conditions. We demonstrate that our mechanisms are effective to protect the SoC while increasing the overall performance. View full abstract»

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  • Security-Aware Modeling and Efficient Mapping for CAN-Based Real-Time Distributed Automotive Systems

    Publication Year: 2015 , Page(s): 11 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (491 KB) |  | HTML iconHTML  

    Security has become a critical issue for automotive electronic systems. To protect against attacks, security mechanisms have to be applied, but the overhead of those mechanisms may impede system performance and cause violations of design constraints. To remedy this problem, we proposed an integrated mixed integer linear programming (MILP) formulation that is the first to address both security and safety constraints during system mapping for controller area network (CAN) based systems . However, its signal-based security constraints do not fully reflect real security requirements, and its objective function is to minimize functional path latencies rather than minimize security risk. Furthermore, its MILP-based approach has high computation complexity. In this work, we present a new formulation that defines path-based security constraints and minimizes security risk directly, and propose a new heuristic algorithm to solve the formulation efficiently. Experiments on an industrial example show that our new algorithm achieves comparable solution quality as the MILP-based approach with much better efficiency. View full abstract»

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  • Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems

    Publication Year: 2015 , Page(s): 15 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (903 KB) |  | HTML iconHTML  

    A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustained during intermittent supply. The approach has a low energy and time overhead which is achieved by reactively hibernating: saving system state only once, when power is about to be lost, and then sleeping until the supply recovers. We validate the approach experimentally on a processor with FRAM nonvolatile memory, allowing it to reactively hibernate using only energy stored in its decoupling capacitance. When compared to a recently proposed technique, the approach reduces processor time and energy overheads by 76%-100% and 49%-79% respectively. View full abstract»

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  • Exploiting Partially-Forgetful Memories for Approximate Computing

    Publication Year: 2015 , Page(s): 19 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB) |  | HTML iconHTML  

    While the memory subsystem is already a major contributor to energy consumption of embedded systems, the guard-banding required for masking the effects of ever increasing manufacturing variations in memories imposes even more energy overhead. In this letter, we explore how partially-forgetful memories can be used by exploiting the intrinsic tolerance of a vast class of applications to some level of error for relaxing this guard-banding in memories. We discuss the challenges to be addressed and introduce relaxed cache as an exemplar to address these challenges for partially-forgetful SRAM caches. Preliminary results show how adapting guard-bands to application characteristics can help the system save significant amount of cache leakage energy (up to 74%) while still generating acceptable quality results. View full abstract»

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  • Scheduling Dynamic Hard Real-Time Task Sets on Fully and Partially Reconfigurable Platforms

    Publication Year: 2015 , Page(s): 23 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (637 KB) |  | HTML iconHTML  

    Reconfigurable systems are increasingly being employed in a large class of today's heterogeneous real-time embedded systems which often demand satisfaction of stringent timeliness constraints. However, executing a set of hard real-time applications on reconfigurable systems such that all timing constraints are satisfied while also allowing efficient resource utilization requires effective scheduling, mapping and admission control strategies. This letter presents methodologies for scheduling periodic hard real-time dynamic task sets on fully and partially reconfigurable field-programmable gate arrays (FPGAs). The floor of the FPGA is assumed to be statically equipartitioned into a set of homogeneous tiles (each of which act as individual processing elements or PEs) such that any arbitrary task of the given task set may be feasibly mapped into the area of a given tile. Experimental results reveal that the proposed algorithms are able to achieve high resource utilization with low task rejection rates over a variety of simulation scenarios. View full abstract»

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  • Task-Aware Interrupt Controller: Priority Space Unification in Real-Time Systems

    Publication Year: 2015 , Page(s): 27 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    In the development of real-time systems, predictability is often hindered by technological factors which break the timing abstractions offered by real time operating systems (RTOSs); namely, the priority space separation between threads and interrupts induces the rate-monotonic problem. Software approaches have tackled this issue, attempting to unify the priority space with varying degrees of success. We present a hardware approach to the problem: unifying the priority space at the interrupt handling subsystem, predictability is greatly enhanced with minimum software modifications. Our solution provides the interrupt controller with awareness of the currently running task's priority making the solution independent of the used operating system. We show how our approach is minimally intrusive at hardware architecture level and provides benefits beyond the capabilities of previous approaches. Our technique shows a 0.05% run-time overhead if no interrupts occur, and run-time reduction proportional to interrupt rate for rates higher than 5 per s, for a interrupt workload around 0.07 ms. View full abstract»

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  • Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip

    Publication Year: 2015 , Page(s): 31 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (791 KB) |  | HTML iconHTML  

    This letter analyses and compares on-chip interfaces for hardware/software communications in the Zynq-7000 all programmable systems-on-chip. Many experiments were carried out to evaluate the exchange of data between the processing system and the programmable logic through general-purpose and high-performance ports; the experiments were conducted for both standalone and Linux applications. The results enable the most effective interfaces for specific types of data to be identified and the effectiveness of Zynq-based hardware accelerators to be assessed. View full abstract»

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  • IEEE membership can help you reach your personal goals

    Publication Year: 2015 , Page(s): 35
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  • Expand your professional network with IEEE

    Publication Year: 2015 , Page(s): 36
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  • IEEE Embedded Systems Letters information for authors

    Publication Year: 2015 , Page(s): C3
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  • [Blank page - back cover]

    Publication Year: 2015 , Page(s): C4
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Aims & Scope

The IEEE EMBEDDED SYSTEMS LETTERS (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Krithi Ramamritham
Department of Computer Science and Engineering
Indian Institute of Technology Bombay

DEPUTY EDITOR-IN-CHIEF
Catherine Gebotys
Department of Electrical and Computer Engineering
University of Waterloo