Formal Methods in Computer Aided Design, 2007. FMCAD '07

11-14 Nov. 2007

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  • Formal Methods in Computer Aided Design - Cover

    Publication Year: 2007, Page(s): c1
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  • Formal Methods in Computer Aided Design - Title page

    Publication Year: 2007, Page(s):i - iii
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  • Formal Methods in Computer Aided Design - Copyright notice

    Publication Year: 2007, Page(s): iv
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  • Formal Methods in Computer Aided Design - TOC

    Publication Year: 2007, Page(s):v - vii
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  • Preface

    Publication Year: 2007, Page(s): viii
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  • Organizing Committee

    Publication Year: 2007, Page(s): ix
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  • Program Committee

    Publication Year: 2007, Page(s): x
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  • Referees

    Publication Year: 2007
    Cited by:  Papers (1)
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  • Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC

    Publication Year: 2007, Page(s):3 - 12
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    When model-checking reports that a property holds on a model, vacuity detection increases user confidence in this result by checking that the property is satisfied in the intended way. While vacuity detection is effective, it is a relatively expensive technique requiring many additional model-checking runs. We address the problem of efficient vacuity detection for Bounded Model Checking (BMC) of L... View full abstract»

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  • Improved Design Debugging Using Maximum Satisfiability

    Publication Year: 2007, Page(s):13 - 19
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (185 KB) | HTML iconHTML

    In today's SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sources in designs automatically. Unfortunately, the capacity and performance of such automated techniques must be considerably extended for industrial applicability. This work aims to improve the performance of current state-of-t... View full abstract»

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  • Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification

    Publication Year: 2007, Page(s):20 - 26
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB) | HTML iconHTML

    Automatic synchronization (or reset) of sequential synchronous circuits is considered one of the most challenging tasks in the domain of formal sequential equivalence verification of hardware designs. Earlier attempts were based on Binary Decision Diagrams (BDDs) or classical reachability analysis, which by nature suffer from capacity limitations. A previous attempt to attack this problem using no... View full abstract»

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  • Boosting Verification by Automatic Tuning of Decision Procedures

    Publication Year: 2007, Page(s):27 - 34
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from the artificial intelligence (AI) community suggest that this tuning process can be automated, and that doing so can lead to significant performance improvements; furthermore, automated parameter optimization can provide ... View full abstract»

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  • Verifying Correctness of Transactional Memories

    Publication Year: 2007, Page(s):37 - 44
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    We show how to verify the correctness of transactional memory implementations with a model checker. We show how to specify transactional memory in terms of the admissible interchange of transaction operations, and give proof rules for showing that an implementation satisfies this specification. This notion of an admissible interchange is a key to our ability to use a model checker, and lets us cap... View full abstract»

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  • Algorithmic Analysis of Piecewise FIFO Systems

    Publication Year: 2007, Page(s):45 - 52
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    Systems consisting of several components that communicate via unbounded perfect FIFO channels (i.e. FIFO systems) arise naturally in modeling distributed systems. Despite well-known difficulties in analyzing such systems, they are of significant interest as they can describe a wide range of communication protocols. Previous work has shown that piecewise languages play an important role in the stud... View full abstract»

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  • Transaction Based Modeling and Verification of Hardware Protocols

    Publication Year: 2007, Page(s):53 - 61
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior of hardware. In mapping such specifications into hardware, designers often decompose each specification transition into sequences of implementation transitions taking one clock cycle each. Some implementation transitions... View full abstract»

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  • Automating Hazard Checking in Transaction-Level Microarchitecture Models

    Publication Year: 2007, Page(s):62 - 65
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (203 KB) | HTML iconHTML

    Traditional hardware modeling using RTL presents a time-stationary view of the design state space which can be used to specify temporal properties for model checking. However, highlevel information in terms of computation being performed on units of data (transactions) is not directly available. In contrast, transaction-level microarchitecture models view the computation as sequences of (data-stat... View full abstract»

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  • Computing Predicate Abstractions by Integrating BDDs and SMT Solvers

    Publication Year: 2007, Page(s):69 - 76
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (205 KB) | HTML iconHTML

    The efficient computation of exact abstractions of a concrete program for a given set of predicates is key to the efficiency of Counter-Example Guided Abstraction-Refinement (CEGAR). Recent work propose the use of DPLL-based SMT solvers, modified into enumerators. This technique has been successfully applied in the realm of software, where a control flow graph is available to direct the exploratio... View full abstract»

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  • Induction in CEGAR for Detecting Counterexamples

    Publication Year: 2007, Page(s):77 - 84
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB) | HTML iconHTML

    Induction has been studied in model checking for proving the validity of safety properties, i.e., showing the absence of counterexamples. To our knowledge, induction has not been used to refute safety properties. Existing algorithms including bounded model checking, predicate abstraction, and interpolation are not efficient in detecting long counterexamples. In this paper, we propose the use of in... View full abstract»

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  • Lifting Propositional Interpolants to the Word-Level

    Publication Year: 2007, Page(s):85 - 89
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    Craig interpolants are often used to approximate inductive invariants of transition systems. Arithmetic relationships between numeric variables require word-level interpolants, which are derived from word-level proofs of unsatisfiability. While word-level theorem provers have made significant progress in the past few years, competitive solvers for many logics are based on flattening the word-level... View full abstract»

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  • Global Optimization of Compositional Systems

    Publication Year: 2007, Page(s):93 - 100
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    Embedded systems typically consist of a composition of a set of hardware and software IP modules. Each module is heavily optimized by itself. However, when these modules are composed together, significant additional opportunities for optimizations are introduced because only a subset of the entire functionality is actually used. We propose COSE-a technique to jointly optimize such designs. We use ... View full abstract»

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  • Cross-Entropy Based Testing

    Publication Year: 2007, Page(s):101 - 108
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    In simulation-based verification, we check the correctness of a given program by executing it on some input vectors. Even for medium-size programs, exhaustive testing is impossible. Thus, many errors are left undetected. The problem of increasing the exhaustiveness of testing and decreasing the number of undetected errors is the main problem of software testing. In this paper, we present a novel a... View full abstract»

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  • Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation

    Publication Year: 2007, Page(s):111 - 118
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (217 KB) | HTML iconHTML

    In this paper, we present AutoGSTE, a comprehensive approach to automatic abstraction refinement for generalized symbolic trajectory evaluation (GSTE). This approach addresses imprecision of GSTE's quaternary abstraction caused by underconstrained input circuit nodes, quaternary state set unions, and existentially quantified-out symbolic variables. It follows the counterexample-guided abstraction ... View full abstract»

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  • A Logic for GSTE

    Publication Year: 2007, Page(s):119 - 126
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (231 KB) | HTML iconHTML

    The formal hardware verification technique of Generalized Symbolic Trajectory Evaluation (GSTE) traditionally uses diagrams called assertion graphs to express properties. Although the graphical nature of assertion graphs can be useful for understanding simple properties, it places limitations on formal reasoning. Clean reasoning is important for high-level verification steps, such as property deco... View full abstract»

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  • Automatic Abstraction in Symbolic Trajectory Evaluation

    Publication Year: 2007, Page(s):127 - 135
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    Symbolic trajectory evaluation (STE) is a model checking technology based on symbolic simulation over a lattice of abstract state sets. The STE algorithm operates over families of these abstractions encoded by Boolean formulas, enabling verification with many different abstraction cases in a single modelchecking run. This provides a flexible way to achieve partitioned data abstraction. It is usual... View full abstract»

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  • A Coverage Analysis for Safety Property Lists

    Publication Year: 2007, Page(s):139 - 145
    Cited by:  Papers (22)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (161 KB) | HTML iconHTML

    We present a coverage analysis that can be used in property-based verification. The analysis helps identifying "forgotten cases"; scenarios where the property list under analysis does not constrain a certain output at a certain point in time. These scenarios can then be manually investigated, possibly leading to new, previously forgotten properties being added. As there often exist cases in which ... View full abstract»

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