# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2018, Page(s): C2
| PDF (656 KB)
• ### Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions

Publication Year: 2018, Page(s):2965 - 2978
Cited by:  Papers (4)
| | PDF (1960 KB) | HTML

The interaction between technology and healthcare has a long history. However, recent years have witnessed the rapid growth and adoption of the Internet of Things (IoT) paradigm, the advent of miniature wearable biosensors, and research advances in big data techniques for effective manipulation of large, multiscale, multimodal, distributed, and heterogeneous data sets. These advances have generate... View full abstract»

• ### Acknowledgment of Reviewers—2018

Publication Year: 2018, Page(s):2979 - 2985
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• ### Efficient Hierarchical Performance Modeling for Analog and Mixed-Signal Circuits via Bayesian Co-Learning

Publication Year: 2018, Page(s):2986 - 2998
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With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling acc... View full abstract»

• ### Exploiting Oscillator Arrays As Randomness Sources for Cryptographic Applications

Publication Year: 2018, Page(s):2999 - 3007
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This paper shows how arrays of coupled resonant oscillators can provide wildly disordered phase responses corresponding to nonsynchronized regimes. The unpredictability of their time response makes oscillator arrays attractive randomness sources for cryptographic applications. We describe a possible implementation of a random number generator (RNG) combining the proposed randomness source with a f... View full abstract»

• ### Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes

Publication Year: 2018, Page(s):3008 - 3019
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Secure masking schemes have been proven in theory to be secure countermeasures against side-channel attacks. The security framework proposed by Ishai, Sahai, and Wagner, known as the Ishai–Sahai–Wagner scheme, is one of the most acceptable secure models of the existing$d$th-order masking schemes, where View full abstract»

• ### Hardware Protection via Logic Locking Test Points

Publication Year: 2018, Page(s):3020 - 3030
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Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of ... View full abstract»

• ### An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata

Publication Year: 2018, Page(s):3031 - 3041
Cited by:  Papers (1)
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Quantum-dot cellular automata (QCA) are an emerging field-coupled nanotechnology with remarkable performance and energy efficiency. In order to enable the exploration of this technology, we propose a model for the logic synthesis of QCA circuits that, for the first time, considers and abstracts all main physical aspects—in particular, energy dissipation. To this end, we review in detail how energy... View full abstract»

• ### AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips

Publication Year: 2018, Page(s):3042 - 3055
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Flow-based microfluidic biochips are promising with significant applications for automating and miniaturizing laboratory procedures in biochemistry. Automated design methods for flow-based microfluidic biochips are becoming increasingly important due to the advancement in both integration scale and design complexity for complicated biochemical applications. Though the multilayer soft lithography f... View full abstract»

• ### An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding

Publication Year: 2018, Page(s):3056 - 3066
Cited by:  Papers (1)
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Stochastic computing (SC) is a promising approach for low-power and low-cost applications with the added benefit of high error tolerance. However, the high overhead of generating stochastic bitstreams can offset the advantages of SC especially when a large number of bitstreams are needed. In this paper, we propose a new stochastic number generator (SNG) that significantly reduces area and energy w... View full abstract»

• ### NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Publication Year: 2018, Page(s):3067 - 3080
Cited by:  Papers (1)
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Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep learning algorithms. In this paper, we developed NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream... View full abstract»

• ### Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms

Publication Year: 2018, Page(s):3081 - 3094
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This paper presents a dynamically reconfigurable processing array named Anole for symmetric-key algorithms. Processing elements and the interconnections between them are designed to support various block and stream ciphers. Without affecting flexibility, three key techniques are presented to increase energy efficiency (throughput/power, the number of operations per unit energy consumption) and are... View full abstract»

• ### Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs

Publication Year: 2018, Page(s):3095 - 3108
| | PDF (1999 KB) | HTML

Dynamic voltage scaling (DVS) is one of the most effective ways to reduce integrated circuit power. However, the programmability of field programmable gate arrays (FPGAs) means that the critical paths depend on the application configured into the FPGA and this makes DVS more difficult. We propose a DVS technique that is able to determine the minimum safe\$... View full abstract»

• ### Stochastic Circuit Synthesis by Cube Assignment

Publication Year: 2018, Page(s):3109 - 3122
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Stochastic computing (SC) is an unconventional computation paradigm, in which digital circuits are adopted to compute on stochastic bit streams. The value represented by a stochastic bit stream is the probability of obtaining a one in the stream. Stochastic circuits are highly tolerant to bit flip errors. Compared to the conventional binary computing, SC can perform complicated arithmetic computat... View full abstract»

• ### The MTA: An Advanced and Versatile Thermal Simulator for Integrated Systems

Publication Year: 2018, Page(s):3123 - 3136
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Fast and accurate thermal analysis is crucial for determining the propagation of heat and tracking the formation of hotspots in integrated circuits (ICs). Existing academic thermal analysis tools primarily use compact models to accelerate thermal simulations but are limited to linear problems on relatively simple circuit geometries. The Manchester Thermal Analyzer (MTA) is a comprehensive tool tha... View full abstract»

• ### Fast Electromigration Immortality Analysis for Multisegment Copper Interconnect Wires

Publication Year: 2018, Page(s):3137 - 3150
Cited by:  Papers (1)
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In this paper, we present a novel and fast electromigration (EM) immortality check for general multisegment interconnect wires. Instead of using current density as the key parameter, as in traditional EM analysis methods based on Black’s equation and the Blech limit, the new method estimates the EM-induced steady-state stress in general multisegment copper interconnect wires based on a novel param... View full abstract»

• ### A Data-Driven Verilog-A ReRAM Model

Publication Year: 2018, Page(s):3151 - 3162
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The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model... View full abstract»

• ### Provably Fast and Near-Optimum Gate Sizing

Publication Year: 2018, Page(s):3163 - 3176
| | PDF (1200 KB) | HTML

We present a new approach for the cell selection problem based on a resource sharing formulation, which is a specialization of Lagrangian relaxation with multiplicative weight updates. For the convex continuous gate sizing problem, we can prove fast polynomial running times. This theoretical result also gives some justification to previous heuristic multiplicative weight update methods. For the di... View full abstract»

• ### Testing 3D-SoCs Using 2-D Time-Division Multiplexing

Publication Year: 2018, Page(s):3177 - 3185
| | PDF (1976 KB) | HTML

Through-silicon vias (TSVs) are used as high-speed vertical interconnects between dies in a 3-D system-on-a-chip (SoC). However, their speed cannot be exploited during test application due to inherent limitations of the scan-chains of the cores, which prevent the use of high shift frequencies during the scan-in/out operations. Moreover, due to their high area cost, only a limited number of TSVs ca... View full abstract»

• ### Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function

Publication Year: 2018, Page(s):3186 - 3197
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Physical unclonable functions (PUFs) have broad application prospects in the field of hardware security. Like faults in general-purpose circuits, faults may also occur in PUFs. Fault diagnosis plays an important role in the yield learning process. Traditional fault diagnosis methods are based on comparing the fault-free responses of a design and the failing responses of chips. However, different m... View full abstract»

• ### SAT-Based Fault Equivalence Checking in Functional Safety Verification

Publication Year: 2018, Page(s):3198 - 3205
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Detecting equivalence classes of injected faults for functional verification of electronic systems is an important task because it helps reducing the number of faults to qualify a verification environment, and hence, improves the performance of qualification process and the validation time required for large-scale electronic systems. This paper describes an efficient way of detecting equivalent in... View full abstract»

• ### Improved Synthesis of Compressor Trees in High-Level Synthesis for Modern FPGAs

Publication Year: 2018, Page(s):3206 - 3210
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In this paper, an approach to synthesize compressor trees in high-level synthesis is proposed. We target the modern field-programmable gate arrays, which integrate carry chains and support fast ternary adders. Two main improvements are achieved in our approach: 1) based on the proposed modified bitmask analysis, we perform bit-level numerical optimizations to shrink the scale of generated compress... View full abstract»

• ### Assessing Layout Density Benefits of Vertical Channel Devices

Publication Year: 2018, Page(s):3211 - 3215
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Vertical channel devices have been considered as promising candidates for sub-5 nm regime for the reduced area and large driving current. Several styles of layout designs and fabrication details of vertical channel devices have been proposed. However, due to the fast-changing manufacturing constraints for the advanced devices, the most efficient layout structures are still yet to be explored. In t... View full abstract»

• ### Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis

Publication Year: 2018, Page(s):3216 - 3220
| | PDF (1092 KB) | HTML

When multiprocessor system-on-chip designs are subjected to aggressive scaling of the processing technology, severe thermal effects will influence the performance, power, and reliability of integrated circuits (ICs). Hence, IC designers employ mesh-based transient thermal analysis (MTTA) to effectively predict the variations and distribution of temperatures in a chip during the early stages of IC ... View full abstract»

## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Rajesh Gupta

University of California, San Diego

Computer Science and Engineering

9500 Gilman Drive

La Jolla California 92093, USA

gupta@cs.ucsd.edu