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Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996

Date 12-14 Nov. 1996

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Displaying Results 1 - 25 of 92
  • ASMC 96 Invited Speakers [biographies]

    Publication Year: 1996 , Page(s): 470 - 479
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    Freely Available from IEEE
  • IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings

    Publication Year: 1996
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    Freely Available from IEEE
  • The development and optimization of the photoresist module qualification procedure

    Publication Year: 1996 , Page(s): 297 - 302
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    A new technique for qualifying and monitoring the photoresist module was optimized. Test wafers with an etched SRAM pattern were inspected before and after photoresist processing. Inspections were performed using an OSI IQ-165 patterned wafer inspection system that employs optical pattern filtering. This system is capable of increasing sensitivity without increasing inspection time. Defect source analysis (KLA 2551) was used to identify and map the defects added by the photoresist module. This technique was compared to the traditional photoresist qualification procedure that evaluates resist patterned on bare silicon wafers View full abstract»

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  • Defect reduction and cost savings through re-inventing RCA cleans

    Publication Year: 1996 , Page(s): 308 - 313
    Cited by:  Patents (4)
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    RCA cleans, (also referred to as SC1 and SC2 cleans) have been used in semiconductor manufacturing for decades. These solutions, as developed by Kern and Puotinen in 1965, are multi-purpose surface treatments. If used as originally developed, they are effective at both organic and metallic contamination control, and are viewed as innocuous to silicon based surfaces. Only recently have new processing conditions been explored. Historically, these mixtures of water, hydrogen peroxide, and either ammonium hydroxide (for the SC1 solution) or hydrochloric acid (for the SC2 solution), were mixed at a 5:1:1 and 6:1:1 ratio respectively and used at temperatures of 70-80 degrees C. This paper presents a comprehensive study using surface analysis and inspection techniques to test residue removal, silicon surface roughening, silicon dioxide etch rates, and particle removal efficiency due to the effects of chemical concentration and temperature. Impinging high-frequency sonic energy onto the wafer surface at different wafer to wafer spacing in the processing cassette is also studied. The authors have found that lower concentration SC1 and SC2 solutions, in concert with “megasonic” energy, leads to higher particle cleaning efficiency, excellent residue removal, reduced silicon surface roughening, and reduced chemical usage in several types of processing equipment. These effects add up to reduced semiconductor device defect densities at a net lower cost. Electrical test data on both DRAM and micro-processors are presented View full abstract»

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  • Photocluster productivity improvement

    Publication Year: 1996 , Page(s): 13 - 16
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    This paper describes improvements being implemented in a multi-technology, multi-partnumber IBM semiconductor fabricator to increase photocluster output. The work of various teams is presented, which have generated a host of enhancements, including a customized logistics system, host computer control, continuous lot chaining, a work-in-process (WIP) and reticle tracking system, area alarms for tool stoppages, staffing based on activity analysis, operator coverage improvements guided by delays determined from host control data and alignment assist reductions guided by host control data. Photocluster productivity has increased 35% since these changes were begun and more improvement is anticipated View full abstract»

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  • Fluorine induced formation of intermetal dielectric defects

    Publication Year: 1996 , Page(s): 303 - 307
    Cited by:  Patents (3)
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    Defects were first observed on engineering test wafers during Contact Photolithography ADI (After Develop Inspection). The defects had the appearance of large white spots, which were several microns in diameter. SEM and TEM studies revealed that the defects were delaminations at the interface between the thermal oxide and the TEOS at the contact module of the wafer process. The results from defect partitioning showed the defects first appeared after high temperature BPSG anneal. It was also observed that only the first one or two wafers in a lot had defects. Chemical contamination analysis using SIMS identified high fluorine concentrations. The results showed that the fluorine concentration of the first wafer through the TEOS process was >30% higher than the rest of the wafers in the lot. Several experimental matrices were designed and conducted to quickly contain the problem, to investigate the defect mechanisms, and to eliminate the defects. It has been concluded that the fluorine outgassing from the P + implanted area (BF2 implant) during high temperature BPSG anneal is the major mechanism of the defect phenomena. TEOS chamber precoating has been shown to reduce the fluorine integrated concentration of the TEOS film and has eliminated the defects View full abstract»

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  • Reduction of shorts between polysilicon word lines on a 4 Meg DRAM product

    Publication Year: 1996 , Page(s): 276 - 280
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    A significant reduction in defects in a polysilicon level was achieved by a team of process and diagnostic engineers. This paper will describe the methodology. Electrical measurements on a defect test site were used together with surface particle counter data and automated optical inspection to understand the problems and determine the success of various actions. Improvements were made at the oxidation, polysilicon deposition, anneal, photolithography, and RIE operations View full abstract»

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  • Production use of an integrated automatic defect classification (ADC) system operating in a laser confocal/white light imaging defect review station

    Publication Year: 1996 , Page(s): 107 - 111
    Cited by:  Papers (4)
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    This paper reports results obtained using a fully automatic defect classification package integrated in the system processor of a Laser Confocal/White Light Defect Review Tool. This system classifies defects utilizing algorithms which automatically load a cassette of wafers previously scanned by an Automatic Defect Inspection tool (ADI), aligns the wafers, and image processes to re-detect the defect. The defect region image is then analyzed for its characterization content, and the results matched with a data base of previously stored examples. System calibration is performed by presenting the system with a series of examples of each type of defect, and is edited with on-line tools provided for that purpose. We report results using the system in a production environment on a series of process levels. This effort is primarily with wafers containing logic circuitry (nonrepeating pattern). Accuracy obtained with white light only imaging is reported, as are improvements when laser confocal imaging (3-D, enhanced resolution) is added. We report also studies of optical and mechanical components of the microscope system which are critical to automatic guidelines for implementation of ADC in the production environment View full abstract»

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  • Waferless pattern recognition recipe creation using StatTrax

    Publication Year: 1996 , Page(s): 353 - 358
    Cited by:  Papers (1)
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    Motorola MOS-12 uses Tencor UV-1050 and FT-750 Film Thickness probes for on product measurements at many steps in the fabrication process. Master recipes are manually created for the first mask set of any new process flow. By utilizing a standard scribe grid structure, recipes for subsequent mask sets are created by copying the master recipes then making changes to the coordinates in the die map and pattern recognition sections of each recipe. The ability to create recipes this way reduces engineering time required for new product introduction and significantly reduces cycle time for lead lots. The method provides the best recipe integrity possible and allows the elimination of costly test wafers View full abstract»

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  • Throughput of steppers with off-axis illuminators: analysis and experiments

    Publication Year: 1996 , Page(s): 54 - 63
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    As manufacturing critical dimensions continue to shrink towards 0.35 μm, the exposure of IC critical levels requires increasingly effective techniques. Demand for such techniques facilitates acceptance of off-axis illumination as a way to better control the process window of 0.35 μm design rule. We focus our attention on issues related to optimization of exposure related factors influencing stepper throughput. We analyzed exposure conditions of one critical level commonly encountered in a variety of IC design. First, we present the result of process modeling and optimization of the critical level exposure. We then review the results of extensive proof-of-principle work done in support of modeling View full abstract»

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  • A systematic team approach for improving LPCVD silicon nitride reactor performance

    Publication Year: 1996 , Page(s): 69 - 75
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    Silicon nitride, often used to define the device active area, is a critical film with a long history in the semiconductor industry. The film is typically formed in a Low Pressure Chemical Vapor Deposition (LPCVD) reactor. As device geometries shrink below 0.5 μm, the need for repeatable nitride particle control is essential to yielding product. Achieving consistent uptime on these LPCVD reactors is equally important to meet increasing productivity requirements. This paper demonstrates how the performance of two horizontal silicon nitride reactors was greatly improved and particle excursions were reduced through a series of process and hardware improvements developed by a team of engineers and technicians. The team started by identifying all known process and equipment failures. Next potential solutions for the failures were developed. The team utilized a systematic approach so that both technical and practical issues were addressed. The potential solutions were ranked and then implemented based on the ones which gave the most return on investment. The most significant technical problem addressed was the effect of the pumpdown delay following door seal on particle performance. Many of the solutions were associated with upgrades that reduced the time it takes for the system to begin pumping down from atmospheric pressure. As a result the number of particle excursions were reduced by a factor of three. Other hardware upgrades were done to reduce intermittent pumpdown and ventup failures. A 40% improvement was seen in the performance of the two nitride systems after the solutions were implemented View full abstract»

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  • Quintuple ramp up slope by implementing cross-functional, self-directed work teams

    Publication Year: 1996 , Page(s): 436 - 441
    Cited by:  Papers (5)
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    The 8-inch Advanced Semiconductor Line (ACL) in Essonnes-Corbeil, France is jointly run by Siemens and IBM with 16 MB DRAMs as the main product. Due to the increasing demand in 16 MB chips, it was decided to ramp up the line capacity by 70% between January and July 96. Although the tool installation happened as planned, the increase in daily going rate (DGR) was by a factor of 2 to 3 too small to meet the aggressive chips out plan for 96. A line analysis showed that the ramp up performance was mainly restricted by two reasons: First not reacting fast enough to line pinch points and second not synchronizing the “4 partners” (workforce, wafer flow, tool-set and process/business procedures) in an optimized way. To overcome those limitations, it was decided to install for each technology so-called productivity teams, which consist of a cross-functional selection of operators, technicians and engineers. The teams are responsible for problem localization as well as definition, installation and follow-ups of action plans, decision trees and check points on a daily basis as well as long term problem analysis. The empowerment of this low hierarchical workforce resulted in a much faster response to line problems and the cross-functional character of the teams propelled the synchronisation of the 4 partners. Two weeks after implementing the teams the line ramp up slope was increased by a factor of 5 and reached a peak value of DGR ramp up speed corresponding to 700 WSPW per month. 6 weeks after the introduction of productivity teams the DGR performance had recovered to the plan and is now (August 96) 3% above plan so that ACL expects to deliver significantly above the 96 plan View full abstract»

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  • Abnormal trend detection of sequence-disordered data using EWMA method [wafer fabrication]

    Publication Year: 1996 , Page(s): 169 - 174
    Cited by:  Papers (1)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    In this paper, we focus on the design issues of applying the exponentially weighted moving average (EWMA) chart to end-of-line electrical test data. Since the sequence of end-of-line test data is not the same as the sequence in each process step, an abnormal trend in any of the process steps is more difficult to detect based on end-of-line test data than based on single step process data (if available). Our approach uses EWMA chart because the moving average is able to smooth out the sequence-disordered effect and the weighting factor allows us to choose an effective moving average size. The correlation among weighting factor, detection speed, and sequence-disordered effect is studied. Fab data is used to verify the effectiveness of EWMA chart for detecting process shifts if we appropriately choose the weighting factor based on the derived correlation View full abstract»

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  • Overall fab efficiency [semiconductor manufacturing]

    Publication Year: 1996 , Page(s): 49 - 52
    Cited by:  Papers (4)
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    The constant increase of the capital needed for a semiconductor facility has brought a huge interest in two methodologies: Theory of Constraints (TOC) and Total Productive Maintenance (TPM) which have been shown to be adequate in optimizing the return on capital equipment. This article shows that both methodologies are convergent. The appropriate use of both together can make it possible to maintain productivity improvement rates in the semiconductor business. The Overall Equipment Efficiency (OEE) measurements are the driver metrics for an effective TPM program. OEE measurements are easy to obtain, nevertheless, the analysis of these parameters requires a large amount of accurate data that are difficult to obtain in a production environment. In addition, it needs the dedication of a considerable amount of effort and human resources to improve in all the organizations (production, maintenance, engineering, etc.). It is widely accepted that bottlenecks should be entered in a TPM program, but for non-bottlenecks, it is not easy to determine which machines should enter the program, their target and their impact on the global fab efficiency. In this study we present a systematic method of approaching this problem View full abstract»

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  • Manufacturing scrap reduction team

    Publication Year: 1996 , Page(s): 230 - 232
    Cited by:  Papers (1)
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    In today's highly competitive: marketplace, working better, smarter, and more cost effectively is essential. The scrap created during manufacturing can either sharpen or diminish a company's competitive edge. Customers require that their orders be delivered on time with yield quality that either meets or exceeds specifications. In Hot Process, scrap and hold lots were becoming a very serious problem that affected the manufacturing team's performance, customers orders, and delivery schedule. To alleviate this problem, each project was directed to address its part of this critical defect issue. The Hot Process project with manufacturing production control, acting as an empowered self-directed group, formed a market-driven team for scrap which could help improve production yields and reduce defects. Issues identified by the team included the lack of a unified procedure for documenting scrap, wafer-handling concerns suggested by new and experienced operators, and how best to focus on single wafer scrap and the cause of that scrap, and its correction or prevention. This paper describes the team's plan (or unified assault) to increase yields by reducing defects and how a common accounting procedure was implemented to review existing departmental practices which could result in a common scrap procedure. Also addressed are the several wafer-handling issues which resulted in revised wafer-handling class that more adequately reflects the nature of today's defects and enhances operator understanding of the the underlying costs associated with how scrap affects yield. Finally, this paper discusses the measurement and reporting of our Hot Process scrap team's yield improvements and defect reductions at bimonthly meetings with management View full abstract»

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  • A new chemistry for a high-density plasma etcher that improves etch rate loading on the TiN ARC layer when geometries are below 0.5 micron

    Publication Year: 1996 , Page(s): 328 - 332
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    A series of process tests were conducted on a high density plasma etcher to improve the etch rate loading. Etch rate loading arises mainly from two different factors which are microloading and aspect ratio dependent etch (ARDE). Microloading can be defined as the etch rate non-uniformities due to pattern density variations. ARDE can be explained as etch nonuniformities between lines with different aspect ratios. Microloading is mainly a flow dependent phenomena while ARDE shows dependence on process chemistries as well. In this study, a new chemistry is introduced for etching the titanium nitride (TiN) ARC layer. With the introduction of this new chemistry, microloading for 0.5 micron geometry is improved by almost 50% compared to the values obtained from the baseline process. The new chemistry provides approximately 5:1 selectivity to the underlying oxide, and gives very high selectivity to the aluminum layer. When using this chemistry, the etch rate of the titanium nitride layer is more than a micron per minute. Details of the improvement obtained in etch rate loading and mechanisms that explain the observed trends are provided in the current paper. Different etch chemistries as well as the new chemistry were tried for the titanium nitride ARC layer etch, and a comparative evaluation of the process performance was done based on the different chemistries. Conventional BCl3/Cl2 chemistry was mainly used for etching the aluminum bulk layer underneath it View full abstract»

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  • Partnership for a rapid yield enhancement solution in a manufacturing environment on a 0.65 μm triple level metal device

    Publication Year: 1996 , Page(s): 429 - 435
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    A speed related problem degraded the yield of a 0.65 μm triple level metal device. Reducing the channel length was the most simple and cost effective approach to improve device speed. However, an overly aggressive downsized channel length could also cause device leakage. To determine the optimal channel length with adequate speed performance and without leakage, a series of experiments were run to establish a yield model as a function of channel length and device threshold voltage (Vt). The Vt was varied by adjusting the channel implant dose. Instead of using masks with different sizings, the channel length was varied by adjusting photo exposure time and lightly doped drain (LDD) implant dose. This approach greatly reduced the cost of experiments and shortened the learning cycle. A strong correlation was established by Analysis of Variances (ANOVA) between yield and p-channel transistor length. The range of operational channel length was defined, where higher channel length caused poor speed performance and lower channel length caused device leakage. An interim process with increased photo exposure time was implemented immediately to ensure die shipment quantity and delivery schedule. In parallel, the optimal mask sizing was determined and this mask regenerated such that the original photo exposure when used with this mask would re-center the process. The interim process was then eliminated to streamline manufacturability. The optimized process resulted in significant yield improvement. Strong partnerships were established among device engineering, process engineering, and manufacturing groups to achieve yield enhancement in a timely manner without compromising manufacturability and customer deliveries View full abstract»

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  • Comparison of patterned wafer defect detection tools for general in-line monitors

    Publication Year: 1996 , Page(s): 92 - 99
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Manufacturer specifications for sensitivity and capture efficiency for pattern wafer defect inspection tools are usually based on data obtained under optimum conditions, using substrates with little process variation, and in some cases long inspection times. Requirements for general in-line monitors at most IC production facilities do not require maximum sensitivity. Key requirements at Motorola MOS 12 for general in-line monitors, when there is no previously identified defect type that must be detected, are zero nuisance defects, significant sample size, and reasonable speed and sensitivity. At startup of Motorola MOS 12, three types of pattern wafer defect inspection tools were purchased: KLA 2131, OSI 165, and Tencor 7600. This paper outlines the results of a study comparing defect detection sensitivity and capture rate for the three systems, given our requirements for general in-line monitors. Results from six steps in our process will be presented. This data was used, in part, to develop our strategy for in-line defect monitoring View full abstract»

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  • User group implementation with a U.S. supplier

    Publication Year: 1996 , Page(s): 460 - 464
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    Tool productivity or Overall Equipment Effectiveness (OEE) is an important topic in the semiconductor industry. One strategy for increasing tool productivity involves increasing the reliability of the system. This task can be better accomplished when the factors affecting the reliability parameters are identified, corrected, and communicated. A User's Group allows all users to share data, issues, lessons learned, and best known methods which then provide the foundation for identifying and resolving barriers to productivity. Often, discussion and communication between the users and the supplier can provide an immediate basis for solutions. Further improvements will be made over time in a partnership between the supplier and the users View full abstract»

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  • Cycle time reduction program at ACL

    Publication Year: 1996 , Page(s): 165 - 168
    Cited by:  Papers (5)
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    In this paper we focus on the results of the DRAM production cycle time team with special emphasis on: how does CT translate into productivity; what tools are needed for effective CT analysis including daily going rate (DGR) issues; how to find and how to fight the main CT detractors The results are compared with the real world execution at the SIEMENS/IBM Advanced CMOS line (ACL) in Essonnes-Corbeil View full abstract»

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  • Advanced chemical downstream etch and strip capability

    Publication Year: 1996 , Page(s): 314 - 316
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Semiconductor manufacturing has slowly but surely been moving from wet etch and strip towards all-dry processing. With the advent of dry isotropic chambers on cluster tool platforms, it is now more attractive than ever to integrate several wet/dry steps into a single all-dry sequence. Target applications include isotropic oxide etch, high-selectivity nitride and poly strip and a variety of soft etches for damage, contaminant and residue removal View full abstract»

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  • Automated metrology qualification strategy [IC measurement]

    Publication Year: 1996 , Page(s): 337 - 342
    Cited by:  Papers (1)
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    This paper presents the methodology used to perform qualification of critical dimension (CD) SEM (Scanning Electron Microscope) tools for sub-0.5 μm process control. A submicron pitch standard has been characterized and incorporated into an automated tool calibration and qualification procedure. After first matching individual tools to the standard, daily tool qualification is performed on a CD qualification wafer. SPC (Statistical Process Control) charts are set up to subtract line broadening effects encountered in repeated SEM measurement. The automated calibration and qualification procedures described here permit accurate measurements to be provided as is required for effective metrology support of the modern factory View full abstract»

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  • New software tools accelerate the fab layout process at National Semiconductor

    Publication Year: 1996
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    Summary form only given, as follows. Building a new semiconductor fabrication facility costs over $1 billion, and the cost of rearranging existing facilities on average exceeds $50000 per tool. These costs, plus shrinking lead times from layout concept to implementation in order to speed new product to market, make it critical that the layout designer quickly and effectively evaluate issues affecting the fab layout in order to get the layout right before construction begins. In response to this need, a set of relatively new software tools (collectively called Facility Layout/Relayout Tool, or FLRT) were developed to enable the layout designer to create the best possible layout in the shortest possible time while simultaneously creating effective documentation of the layout process. In addition to accomplishing this goal, the FLRT software has allowed the layout designer to evaluate other decisions, such as the cost/benefits of implementing an automated material handling system (AMHS) versus conventional material movements, and the relative aisle widths required based on the intensity of material flow. The FLRT development was partially sponsored by SEMATECH. This paper discusses how National Semiconductor used FLRT to design the layout for a new 200 mm wafer fabrication facility in South Portland, Maine View full abstract»

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  • Interactive engineering documentation

    Publication Year: 1996
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (40 KB)  

    With the rapid development of the Internet, Intranets and various Internet browsers, companies are now able to link to a multitude of information resources on-line at a much faster and more user friendly manner than ever before. The utilization of this technology is still in its infancy and the possibilities which it offers are numerous. In the realm of Facilities Management AMD is taking advantage of the vast opportunities offered by the flexibility, low cost, speed, and improved communications offered by the development of these tools. This document introduces individuals to the benefits of developing and maintaining an Intranet Engineering Documentation database within the Facilities organization of a company. Emphasis will be placed on six distinct areas: Facilities Systems, Equipment, Drawings, Databases, Costs, and Benefits. This paper outlines AMD's Facility Resource Database written and linked specifically for an existing network server (A Web Server is not mandatory). Material covered includes: conversion of engineering documentation from paper to computer copy and the utilization of Netscape as the navigator, viewer, and linking tool for the various Facilities data, drawings, equipment specifications, and existing databases. When individuals understand the ideas presented in this tutorial, they will have the tools needed to develop similar databases with minimal expenses View full abstract»

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  • Defect reduction through statistical process control and prior-level subtraction analysis

    Publication Year: 1996 , Page(s): 293 - 296
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    This paper discusses the reduction of defects in a nitride etching process using statistical process control (SPC). How defects are reduced in a contact process is also described View full abstract»

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