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[1992] Proceedings 29th ACM/IEEE Design Automation Conference

8-12 June 1992

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Displaying Results 1 - 25 of 131
  • Certified timing verification and the transition delay of a logic circuit

    Publication Year: 1992, Page(s):549 - 555
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (737 KB)

    The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in the circuit. This result is used to derive a procedure which directly computes the transition delay of a circuit. Experimental results of applying the transition delay computation procedure to a number of benchm... View full abstract»

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  • The role of long and short paths in circuit performance optimization

    Publication Year: 1992, Page(s):543 - 548
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (482 KB)

    The authors consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. To develop the timing of the circuit, they use a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. The bounds on the clock period can alternatively be viewed as optimization objectives. At the physica... View full abstract»

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  • Iterative and adaptive slack allocation for performance-driven layout and FPGA routing

    Publication Year: 1992, Page(s):536 - 542
    Cited by:  Papers (39)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors gives a generalization, called the limit-bumping algorithm (LBA), of a procedure of H. Youssef et al. (1990) that transforms initial connection delays into upper limits on delay suitable for performance-driven layout. LBA is a simple way to distribute slacks using arbitrary allocation functions. It is shown that lower and upper bounds on connection delays can be used in the computation... View full abstract»

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  • FARM: an efficient feed-through pin assignment algorithm

    Publication Year: 1992, Page(s):530 - 535
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (459 KB)

    The authors propose an efficient feedthrough pin assignment algorithm, FARM, to minimize the maximum channel density, and at the same time to reduce the wire length and via number. A novel vertical channel routing formulation is devised to model the pin assignment problem. A multirow density minimization followed with a single-row pin assignment is proposed to complete the assignment process. Some... View full abstract»

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  • Power and ground network topology optimization for cell based VLSIs

    Publication Year: 1992, Page(s):524 - 529
    Cited by:  Papers (50)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (462 KB)

    A new power and ground network design problem for cell-based VLSIs is discussed. In contrast to the conventional method, the network topology is optimized, or wiring resource consumption subject to electromigration and voltage drop constraints is minimized. The proposed method has been implemented. Using several examples, the validity of the problem formulation and the solution method was confirme... View full abstract»

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  • Zero skew clock net routing

    Publication Year: 1992, Page(s):518 - 523
    Cited by:  Papers (88)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (506 KB)

    The authors present an algorithm, called the zero skew segment tree method (ZSTM), for the clock net routing problem. To eliminate the lock skew and minimize the total wire length, ZSTM recursively partitions the sink nodes into two subsets which have equal loadings and minimum sum of diameters, and then constructs a zero skew segment tree according to the partitioning result. The final layout of ... View full abstract»

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  • Application-driven design automation for microprocessor design

    Publication Year: 1992, Page(s):512 - 517
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB)

    The authors present an overview of the application-driven design automation system (ADAS) for microprocessor design. ADAS accepts a specification of the instruction set architecture as input, and produces both layout specified in Caltech Intermediate Form, and a reorder table for the language compiler as output. The system spans language design, compiler design, instruction set design, microarchit... View full abstract»

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  • Automated design decision support system

    Publication Year: 1992, Page(s):506 - 511
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    The automated design decision support system (ADDSS) is an ongoing Boeing Helicopters IR&D program to provide a concurrent engineering (CE) design environment for preliminary design. ADDSS research has focused on three components necessary for effective CE: a design representation for structuring and sharing design knowledge; design assessment using attributes as a design language; and an adva... View full abstract»

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  • Design process management for CAD frameworks

    Publication Year: 1992, Page(s):500 - 505
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    The authors introduce a new mechanism for planning and managing the VLSI design process. The design process manager significantly enhances the capabilities of CAD frameworks, relieving designers from dealing with low-level details, thereby allowing them to concentrate on the more innovative aspects of design. A model for representing design processes is described. To demonstrate the suitability of... View full abstract»

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  • A near optimal algorithm for technology mapping minimizing area under delay constraints

    Publication Year: 1992, Page(s):492 - 498
    Cited by:  Papers (45)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (561 KB)

    The authors examine the problem of mapping a Boolean network using gates from a finite size cell library to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. The approach consists of two steps: In the first step, delay functions are computed at all nodes in the network, and in the second step the mapping solution is generated based on the computed d... View full abstract»

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  • LATTIS: an iterative speedup heuristic for mapped logic

    Publication Year: 1992, Page(s):488 - 491
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The author describes heuristic problems for performance optimization of mapped combinational logic, implemented in the system LATTIS (logic area-time tradeoff for integrated systems). LATTIS currently has six transform types: gate repowering, buffer insertion, downpowering of noncritical fanouts of the critical path, gate duplication, DeMorgan's laws, and timing-directed factorization and remappin... View full abstract»

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  • BDDMAP: a technology mapper based on a new covering algorithm

    Publication Year: 1992, Page(s):484 - 487
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB)

    The authors present a technology mapper, BDDMAP, which combines the strengths of rule-based heuristics and algorithmic techniques. Rule-based heuristics or functional matching is invoked to match the type of technology gates for which it is most efficient. The algorithmic part of BDDMAP lies in the covering process. The novel aspects of the covering algorithm are using an anticipative cost functio... View full abstract»

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  • On the circuit implementation problem (combinatorial logic circuits)

    Publication Year: 1992, Page(s):478 - 483
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (445 KB)

    The authors consider the problem of selecting an implementation of each circuit module from a cell library to satisfy overall delay and area, or delay and power requirements. Two versions of the circuit implementation problem, the basic circuit implementation problem and the general circuit implementation problem, are shown to be NP-hard. A pseudo-polynomial-time algorithm for the basic circuit im... View full abstract»

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  • IPDA: interconnect performance design assistant

    Publication Year: 1992, Page(s):472 - 477
    Cited by:  Papers (5)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    IPDA is a generic interconnect performance design assistant that integrates a finite-difference numerical simulation method, linear interpolation algorithm, interactive performance synthesis methodology, and lossless/lossy transmission-line SPICE modeling capability into a spreadsheet-style graphical user interface. The algorithm, implementation, and methodology of IPDA are described and an applic... View full abstract»

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  • Tools to aid in wiring rule generation for high speed interconnects

    Publication Year: 1992, Page(s):466 - 471
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The MetaSim allows multiple simulation studies to be automatically specified, conducted, and analyzed in such a fashion so as to produce wiring rules for layout tools. The authors describe the operation of MetaSim and give an example of its use. One of MetaSim's current engines, Transim, is a convolution simulator that incorporates a robust, rapid, and accurate method for the simulation of coupled... View full abstract»

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  • Challenges and advances in electrical interconnect analysis

    Publication Year: 1992, Page(s):460 - 465
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (463 KB)

    The authors review key issues regarding electrical interconnect analysis (EIA) for VLSI parasitic circuits. They give a general introduction to important aspects for technologies with a variety of performances and then review some issues relating to the state of the art for high-performance chips and packages. For high-performance technologies, the state-of-the-art tools leave a lot to be desired.... View full abstract»

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  • Test-set preserving logic transformations

    Publication Year: 1992, Page(s):454 - 458
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (409 KB)

    Logic transformations that preserve minimal or complete test sets of a combinational circuit are examined. Some basic transformation types are rigorously defined and characterized with respect to test-set preservation. The authors apply the transformations to adder design and show that any complete test set for a two-level adder is preserved on transformation to ripple-carry and carry-lookahead de... View full abstract»

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  • Optimization of primitive gate networks using multiple output two-level minimization

    Publication Year: 1992, Page(s):449 - 453
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (415 KB)

    A novel method for the optimization of a primitive gate network is presented. The author explains why a primitive gate representation may be necessary in certain situations and describes the problems associated with using two-level minimization in that case. He then describes a method for applying two-level minimization for the optimization of a primitive gate network. The approach is based on mul... View full abstract»

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  • Efficient sum-to-one subsets algorithm for logic optimization

    Publication Year: 1992, Page(s):443 - 448
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (519 KB)

    An optimization algorithm, RENO, was proposed by K.C. Chen et al. (1991), in which a given network was minimized by optimally resynthesizing each gate in the network. It is shown that the resynthesis problem in RENO can be transformed into a minimum-cost sum-to-one subset problem based on a given cost function, which is an important problem that often occurs in logic optimization algorithms. Effic... View full abstract»

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  • Coalgebraic division for multilevel logic synthesis

    Publication Year: 1992, Page(s):438 - 442
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB)

    By introducing two Boolean properties into an algebraic division operation, a subset of Boolean division can be performed with approximately the same complexity as the algebraic division implemented in the misII environment. The extended algebraic division algorithm is called coalgebraic division. The experimental results show that the execution time of coalgebraic division is very close to that o... View full abstract»

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  • HLSIM-a new hierarchical logic simulator and netlist converter

    Publication Year: 1992, Page(s):432 - 437
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (351 KB)

    HLSIM is a hierarchical logic simulator that can deal with nested models. HLSIM is intended to simulate large VLSI circuits, including chips. The authors discuss two aspects of the simulator, as an analog-to-digital netlist converter and as a new digital simulator. As a converter, it takes a hierarchical analog ASTAP netlist and supplementary files for the leaf models and creates a digital model o... View full abstract»

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  • Performance evaluation of an event-driven logic simulation machine

    Publication Year: 1992, Page(s):428 - 431
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (267 KB)

    The author evaluates the performance of an event-driven logic simulation machine, called the SP. Since an event-driven machine only schedules gates that have signal-changes on their inputs, it processes fewer gates than the level-sort machine does. However, if the event-driven machine spends too many clocks on dynamic scheduling, the simulation time cannot be reduced. The overhead for dynamic sche... View full abstract»

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  • Zero delay versus positive delay in an incremental switch-level simulator

    Publication Year: 1992, Page(s):424 - 427
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (335 KB)

    The author presents methods used in the implementation of an incremental zero/integer-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model. Zero-delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing provides an ability to model race conditions that do affect the logic. In ex... View full abstract»

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  • Two new techniques for compiled multi-delay logic simulation

    Publication Year: 1992, Page(s):420 - 423
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB)

    The authors describe two techniques for compiled event driven multidelay logic simulation that provide significant performance improvements over interpreted multidelay logic simulation. These two techniques are based on the concept of retargetable branch instructions that can be used to switch segments of code into and out of the instruction stream. The second algorithm, called the shadow techniqu... View full abstract»

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  • Validating discrete event simulations using event pattern mappings

    Publication Year: 1992, Page(s):414 - 419
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The authors introduce a new concept for the validation of discrete event simulations, based on recursively detecting and naming patterns of events. In this methodology, simulation results are presented as a small set of easy-to-understand high-level events. This hierarchical presentation of simulation results greatly reduces the designer's work in browsing through simulation results and detecting ... View full abstract»

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