[1992] Proceedings 29th ACM/IEEE Design Automation Conference

8-12 June 1992

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Displaying Results 1 - 25 of 131
  • Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (14 KB)
    Freely Available from IEEE
  • An interpreter for general netlist design rule checking

    Publication Year: 1992, Page(s):305 - 310
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A new approach to general netlist design rule checking is presented, which has been successfully applied to design for testability rule checking and electrical rule checking. The core of the checker is an interpreter, which performs operations of a set-based calculus. In combination with hierarchy preprocessing by expansion and netlist pattern matching, the interpreter approach is discussed. The i... View full abstract»

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  • Hierarchical pitchmatching compaction using minimum design

    Publication Year: 1992, Page(s):311 - 317
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    A new hierarchical compactor capable of compacting and pitchmatching hierarchically defined layouts is described. The hierarchical compactor can handle most input hierarchies, including multilevel hierarchies, over the cell routing and cell rotations and reflections. The compactor simultaneously compacts the contents of all the cells of the layout hierarchy maintaining the hierarchy of the input l... View full abstract»

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  • A performance driven macro-cell placement algorithm

    Publication Year: 1992, Page(s):147 - 152
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The authors present a new performance driven macro-cell placement algorithm. Placement of modules is guided by a set of upper- and lower-bounds on the net wire lengths. A convex programming algorithm is used to compute a set of upper-bounds on the net wire lengths which will ensure that timing requirements between input and output signals are satisfied. A set of lower-bounds is also computed to co... View full abstract»

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  • Synthesis and simulation of digital systems containing interacting hardware and software components

    Publication Year: 1992, Page(s):225 - 230
    Cited by:  Papers (72)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    The authors consider software and interface synchronization schemes that facilitate communication between system components. They present tools to perform synthesis and simulation of a system description into hardware and software components. A program, Poseidon, is described that performs concurrent event-driven simulation of multiple functional modules implemented either as a program or as behav... View full abstract»

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  • HLSIM-a new hierarchical logic simulator and netlist converter

    Publication Year: 1992, Page(s):432 - 437
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    HLSIM is a hierarchical logic simulator that can deal with nested models. HLSIM is intended to simulate large VLSI circuits, including chips. The authors discuss two aspects of the simulator, as an analog-to-digital netlist converter and as a new digital simulator. As a converter, it takes a hierarchical analog ASTAP netlist and supplementary files for the leaf models and creates a digital model o... View full abstract»

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  • IPDA: interconnect performance design assistant

    Publication Year: 1992, Page(s):472 - 477
    Cited by:  Papers (5)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    IPDA is a generic interconnect performance design assistant that integrates a finite-difference numerical simulation method, linear interpolation algorithm, interactive performance synthesis methodology, and lossless/lossy transmission-line SPICE modeling capability into a spreadsheet-style graphical user interface. The algorithm, implementation, and methodology of IPDA are described and an applic... View full abstract»

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  • A graph theoretic technique to speed up floorplan area optimization

    Publication Year: 1992, Page(s):62 - 68
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    The authors present two algorithms to optimally select implementations for rectangular and L-shaped subfloorplans. The algorithms are designed specifically for the floorplan optimization algorithm given by T.-C. Wang and D.F. Wong (see Proc. 27th ACM/IEEE Des. Autom. Conf., p.180-6 (1990)), but they can also be applied to other algorithms as well. The experimental results, based on incorporating t... View full abstract»

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  • Process independent constraint graph compaction

    Publication Year: 1992, Page(s):318 - 322
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The author describes the DASL symbolic layout system, which is used to create experimental VLSI circuits. The DASL constraint graph compactor requires no user intervention to produce a process-independent design. It also produces results that are electrically correct, e.g., that control the placement of substrate contacts. In other constraint graph compaction if there is nothing to constrain an el... View full abstract»

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  • Fuzzy logic approach to placement problem

    Publication Year: 1992, Page(s):153 - 158
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The authors apply fuzzy reasoning to the placement of sea-of-gate arrays. Fuzzy logic is used to optimize a process of decision making in physical design. Multiple objectives such as utilization of area, routability, and timing were considered simultaneously and balanced by fuzzy logic algorithms. The experiments demonstrated that solutions obtained by fuzzy logic were of much better quality than ... View full abstract»

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  • Routing considerations in symbolic layout synthesis

    Publication Year: 1992, Page(s):682 - 686
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The authors discuss routing styles, including a newly proposed hybrid routing style, in basic silicon-level design for a symbolic layout synthesis tool with practical considerations for design rules and process technology. Methods for systematically adding jogs in the layout to achieve high layout quality are proposed. Algorithms for input/output-pin assignment and for pin-ordering routing that ac... View full abstract»

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  • High-level synthesis with pin constraints for multiple-chip designs

    Publication Year: 1992, Page(s):231 - 234
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The authors describe an approach to multi-chip data path synthesis, given a behavorial description which has already been partitioned into a number of clusters, with the feasibility of clusters determined. The problem is divided into interchip connection determination and scheduling. A heuristic search technique is described for interchip connection determination. A pipelined RTL design consisting... View full abstract»

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  • Test-set preserving logic transformations

    Publication Year: 1992, Page(s):454 - 458
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Logic transformations that preserve minimal or complete test sets of a combinational circuit are examined. Some basic transformation types are rigorously defined and characterized with respect to test-set preservation. The authors apply the transformations to adder design and show that any complete test set for a two-level adder is preserved on transformation to ripple-carry and carry-lookahead de... View full abstract»

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  • Net partitions yield better module partitions

    Publication Year: 1992, Page(s):47 - 52
    Cited by:  Papers (26)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    The authors demonstrate that the dual intersection graph of the netlist strongly captures circuit properties relevant to partitioning. The main contribution of the analysis highlights advantages to using the dual representation of the logic design, and confirming that net structure and interrelationships, rather than module adjacencies, should constitute the primary descriptors of a circuit. In pa... View full abstract»

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  • Coalgebraic division for multilevel logic synthesis

    Publication Year: 1992, Page(s):438 - 442
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    By introducing two Boolean properties into an algebraic division operation, a subset of Boolean division can be performed with approximately the same complexity as the algebraic division implemented in the misII environment. The extended algebraic division algorithm is called coalgebraic division. The experimental results show that the execution time of coalgebraic division is very close to that o... View full abstract»

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  • Superpipelined control and data path synthesis

    Publication Year: 1992, Page(s):638 - 643
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The authors describe a superpipelined control and data path synthesis system. The system can handle pipelined modules in the data path, perform functional pipelining in the data path, and schedule the data path using a pipelined controller. Three control styles-serial, parallel, and pipelined-were implemented. The system automatically picks one depending on the data path, the clock frequency, and ... View full abstract»

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  • Control optimization in high-level synthesis using behavioral don't cares

    Publication Year: 1992, Page(s):657 - 661
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The authors present techniques for optimization of the control part of designs generated by high-level synthesis. The concept of behavioral don't cares is defined and algorithms for extracting behavioural don't care conditions from a high-level description are given. These don't care conditions are used for the optimization of the control logic and the finite-state machine, after high-level synthe... View full abstract»

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  • On the circuit implementation problem [combinatorial logic circuits]

    Publication Year: 1992, Page(s):478 - 483
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The authors consider the problem of selecting an implementation of each circuit module from a cell library to satisfy overall delay and area, or delay and power requirements. Two versions of the circuit implementation problem, the basic circuit implementation problem and the general circuit implementation problem, are shown to be NP-hard. A pseudo-polynomial-time algorithm for the basic circuit im... View full abstract»

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  • New models for four- and five-layer channel routing

    Publication Year: 1992, Page(s):589 - 593
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The author proposes two routing models for the four- and the five-layer routing environments based on the HHVH and HHVHH models, respectively. The layers for horizontal routing and the other for vertical routing are referred to as H and V layers, respectively. Since more layers are available for horizontal routing in the proposed models and the introduced via-violations in the new models are appro... View full abstract»

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  • Validating discrete event simulations using event pattern mappings

    Publication Year: 1992, Page(s):414 - 419
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    The authors introduce a new concept for the validation of discrete event simulations, based on recursively detecting and naming patterns of events. In this methodology, simulation results are presented as a small set of easy-to-understand high-level events. This hierarchical presentation of simulation results greatly reduces the designer's work in browsing through simulation results and detecting ... View full abstract»

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  • Analyzing cycle stealing on synchronous circuits with level-sensitive latches

    Publication Year: 1992, Page(s):393 - 398
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors present a new method to fully explore cycle steal opportunities in the timing analysis for level-sensitive synchronous circuit designs. The algorithm first constructs a latch graph from a timing analysis on the combinational logic, and then it analyzes cycle stealing based on overlay timing relationships among latch nodes. A breadth-first search examines all possible cycle stealing amo... View full abstract»

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  • High-level synthesis from VHDL with exact timing constraints

    Publication Year: 1992, Page(s):188 - 193
    Cited by:  Papers (14)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    The authors present a solution to the interface timing problem in high-level synthesis by requiring that the algorithmic specification must completely determine the interface timing on the basis of cycles. They explain the timing problem and discuss the solution, which is closely related to a specific subset of the very high-speed IC description language (VHDL). This approach has been integrated i... View full abstract»

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  • Canonical embedding of rectangular duals with applications to VLSI floorplanning

    Publication Year: 1992, Page(s):69 - 74
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    The notion of equivalent embedding of rectangular duals is introduced, leading to a new concept of canonical embedding of a rectangular dual; this is a floorplan corresponding to a given neighborhood graph such that the number of directed cycles in its channel digraph is minimum. Strongly maximal rectangular hierarchy (sMRH) in nonslicible floorplans is then defined. The canonical form of any arbi... View full abstract»

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  • A new hierarchical layout compactor using simplified graph models

    Publication Year: 1992, Page(s):323 - 326
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A new hierarchy-preserving hierarchical compactor which can be used with either 1-D or 2-D leafcell compaction techniques has been developed. The compactor is applicable to hierarchical layouts which consist of a number of arrays of identical cells. The hierarchy is maintained throughout the compaction process so that all the instances of a subarray of identical cells have the same shape after com... View full abstract»

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  • Delay fault test generation for scan/hold circuits using Boolean expressions

    Publication Year: 1992, Page(s):159 - 164
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    A new test generation technique for path delay faults in scan/hold type circuits is presented. It uses reduced ordered binary decision diagrams to represent Boolean functions implemented by the subcircuits in a circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit under test and a pair of constraint function... View full abstract»

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