Proceedings Second Working Conference on Asynchronous Design Methodologies

30-31 May 1995

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  • Proceedings Second Working Conference on Asynchronous Design Methodologies

    Publication Year: 1995
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    Freely Available from IEEE
  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • Micronets: a model for decentralising control in asynchronous processor architectures

    Publication Year: 1995, Page(s):190 - 199
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (748 KB)

    Micronets model processor architectures as a network of communicating resources, in contrast to the traditional one of a linear pipeline. Micronets distribute the control to the functional units, which enables the exploitation of fine-grain concurrency between instructions. The overhead due to asynchrony is hidden with the four-phase protocol being used to implement scoreboarding and hazard avoida... View full abstract»

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  • ECSTAC: a fast asynchronous microprocessor

    Publication Year: 1995, Page(s):180 - 189
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (744 KB)

    This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected ... View full abstract»

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  • Asynchronous circuits based on multiple localised current-sensing completion detection

    Publication Year: 1995, Page(s):170 - 177
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    Asynchronous circuits based on Current-Sensing Completion Detection (CSCD) are an efficient alternative to known dual rail coding techniques in terms of area required, operating speed and power consumption. New BiCMOS Current-Sensing Circuits (CSC's) which fully support the advantages of CSCD are presented. Multiple localised CSC's are studied and an example of a 4-bit parallel multiplier is inves... View full abstract»

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  • Testing self-timed circuits using partial scan

    Publication Year: 1995, Page(s):160 - 169
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (852 KB)

    This paper presents a partial scan method for testing both the control and data path parts of macromodule based self-timed circuits for stuck-at faults. Compared with other proposed test methods for testing control paths in self-timed circuits, this technique offers better fault coverage under a stuck-at input model than methods using self-checking properties, and requires fewer storage elements t... View full abstract»

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  • Testing C-elements is not elementary

    Publication Year: 1995, Page(s):150 - 159
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (680 KB)

    We examine stuck-at faults in several gate circuits realizing the C-element. We exhibit circuits with the following phenomena: (a) 50% of single faults do not cause the circuit to halt. (b) Some faults are not detectable by logic tests. (c) A test of length seven is required to detect all detectable single faults. (d) A fault may result in an oscillation. (e) A fault may destroy the speed-independ... View full abstract»

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  • Technology mapping of timed circuits

    Publication Year: 1995, Page(s):138 - 147
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (728 KB)

    This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the design process to optimize the implementation. Our procedure begins with a timed specification and a delay-annotated gate library descri... View full abstract»

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  • Stretching quasi delay insensitivity by means of extended isochronic forks

    Publication Year: 1995, Page(s):99 - 106
    Cited by:  Papers (24)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (548 KB)

    Handshake circuits can be mapped onto QDI circuits using generic standard-cells only. Despite several interesting optimizations, the resulting circuits are large. By extending the isochronic-fork assumption, we arrive at a class of asynchronous circuits that particularly allow efficient realizations of double-rail data paths. This paper defines the extended isochronic fork, discusses its implement... View full abstract»

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  • Hierarchical gate-level verification of speed-independent circuits

    Publication Year: 1995, Page(s):128 - 137
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (844 KB)

    This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment onl... View full abstract»

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  • A hybrid asynchronous system design environment

    Publication Year: 1995, Page(s):91 - 98
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (648 KB)

    A hybrid design scheme for the synthesis of asynchronous circuits is described which exploits the rapid design time achievable using the Tangram silicon complier (developed by Philips), the high performance of 4-phase micropipelines and the use of synchronous design techniques to increase concurrency and therefore performance. Trade-offs between area, power performance and design time are thus sup... View full abstract»

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  • High-level test evaluation of asynchronous circuits

    Publication Year: 1995, Page(s):63 - 71
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (872 KB)

    The present a method for evaluating production fault tests for asynchronous circuits. A novel fault model is defined, based on a high-level circuit description, allowing the evaluation of production tests on the design level. This evaluation method is used in the test generation for an asynchronous 22 k transistor DCC error corrector IC, resulting in a fault coverage of 99.8% View full abstract»

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  • Optimised state assignment for asynchronous circuit synthesis

    Publication Year: 1995, Page(s):118 - 127
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (740 KB)

    This paper presents a new efficient optimised state assignment method for solving complete state coding (CSC) problem that operates purely at the state graph level and is applicable to a broad class of behaviors. This method has been automated and applied to a large set of asynchronous benchmarks and industrial circuits. Compared to existing techniques, this new method achieves significant improve... View full abstract»

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  • Sequencer circuits for VLSI programming

    Publication Year: 1995, Page(s):82 - 90
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    One of the major operations in the VLSI programming language Tangram is the sequencing of computations. A description and critique of the current implementation for this operation is given. Several new implementations are described: one was developed within the SI-algebra framework and the others, based on a count-decode architecture, are the result of an “engineering approach” using a... View full abstract»

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  • Low-latency asynchronous FIFO buffers

    Publication Year: 1995, Page(s):24 - 31
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (516 KB)

    A parallel asynchronous implementation of a FIFO buffer is described and compared with the conventional alternative asynchronous implementation, Sutherland's micropipeline. The parallel design has the potential for significant reductions in propagation delay at the cost of insignificant increases in cycle-time (i.e. reduced throughput) and area. Although in certain applications, e.g. DSP, only hig... View full abstract»

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  • Single-rail handshake circuits

    Publication Year: 1995, Page(s):53 - 62
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (972 KB)

    Single-rail handshake circuits are introduced as a cost effective implementation of asynchronous circuits. Compared to double-rail implementations, the circuits are smaller, faster, and more energy-efficient. Furthermore, in contrast to common belief, all four phases of the four-phase handshake protocol can be productive. An important selling point for single-rail circuits is that they can be impl... View full abstract»

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  • Hades-towards the design of an asynchronous superscalar processor

    Publication Year: 1995, Page(s):200 - 209
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (752 KB)

    This paper uses Hades, a generic processor architecture aimed at single and multiple-instruction-issue asynchronous implementations, to illustrate some of the difficulties encountered in asynchronous processor design. Particular emphasis is placed on a decoupled operand forwarding mechanism which allows the last result of each functional unit to be forwarded to following instructions, yet complete... View full abstract»

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  • Performance evaluation of asynchronous logic pipelines with data dependent processing delays

    Publication Year: 1995, Page(s):4 - 13
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (812 KB)

    Among the claims made concerning the advantages of asynchronous logic are that circuits can take advantage of average case (data dependent) speed rather than worst case speed. Whilst this argument can easily be sustained for a single logic stage its extension to systems consisting of many logic stages has not been widely investigated. This paper reports on investigations into the throughput of asy... View full abstract»

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  • Relative liveness: from intuition to automated verification

    Publication Year: 1995, Page(s):108 - 117
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (876 KB)

    We point out deficiencies of previous treatments of liveness. We define a new liveness condition in two forms: one based on finite trace theory and the other on automata. We prove the equivalence of these two forms. We introduce a safety condition and derive modular and hierarchical verification theorems for both safety and liveness. Finally, we give an algorithm for verifying liveness View full abstract»

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  • A single-rail re-implementation of a DCC error detector using a generic standard-cell library

    Publication Year: 1995, Page(s):72 - 79
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (732 KB)

    We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous... View full abstract»

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  • Designing an asynchronous pipeline token ring interface

    Publication Year: 1995, Page(s):32 - 41
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (976 KB)

    We describe the design of a speed-independent interface based on a pipeline token-ring architecture. The original goal was to build a reliable communication medium, able to tolerate up to two faults in any segment of the ring, to be used in an on-board multicomputer. We believe that the pipeline ring approach can help reduce some negative “analogue” effects inherent in asynchronous bus... View full abstract»

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  • ARAS: asynchronous RISC architecture simulator

    Publication Year: 1995, Page(s):210 - 219
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (772 KB)

    In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this simulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline configuration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, the ... View full abstract»

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  • New CMOS VLSI linear self-timed architectures

    Publication Year: 1995, Page(s):14 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (840 KB)

    The implementation of digital signal processor circuits via self-timed techniques is currently a valid alternative to solve some problems encountered in synchronous VLSI circuits. However, a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously repo... View full abstract»

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  • VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player

    Publication Year: 1995, Page(s):44 - 52
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (796 KB)

    A fully asynchronous Reed-Solomon decoder for the DCC player has been designed in the VLSI programming language Tangram. The main design aim was minimal power dissipation. The design decisions leading to a low-power cost-effective design are discussed. The asynchronous circuit has been fabricated and successfully incorporated in a working DCC system. We estimate that this chip is less than 20% lar... View full abstract»

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