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Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Date 18-21 March 1996

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  • Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems

    Publication Year: 1996
    Save to Project icon | Request Permissions | PDF file iconPDF (184 KB)  
    Freely Available from IEEE
  • Author index

    Publication Year: 1996
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    Freely Available from IEEE
  • Some limitations to speed-independence in asynchronous circuits

    Publication Year: 1996 , Page(s): 104 - 111
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (664 KB)  

    Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements ... View full abstract»

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  • The energy and entropy of VLSI computations

    Publication Year: 1996 , Page(s): 188 - 196
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (788 KB)  

    We introduce the concept of energy index, a measure which can be used to estimate the pourer dissipation of a standard implementation of the high-level specification for an asynchronous circuit. This energy index is related to information-theoretic entropy measures. It is shown how these measures can be used to design low-power circuits View full abstract»

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  • Control resynthesis for control-dominated asynchronous designs

    Publication Year: 1996 , Page(s): 233 - 243
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (796 KB)  

    Syntax directed translation based compilation from high-level concurrent programs has matured significantly over the past few years. They have been applied to significant designs in the domains of digital signal processing and microprocessor designs. For data-path dominated designs, like those found in digital signal processing applications, syntax directed translation approaches have been shown t... View full abstract»

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  • A low-power asynchronous data-path for a FIR filter bank

    Publication Year: 1996 , Page(s): 197 - 207
    Cited by:  Papers (13)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (896 KB)  

    This paper describes a number of design issues relating to the implementation of low-power asynchronous signal processing circuits. Specifically, the paper addresses the design of a dedicated processor structure that implements an audio FIR filter bank which is part of an industrial application. The algorithm requires a fixed number of steps and the moderate speed requirement allows a sequential i... View full abstract»

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  • An efficient algorithm for deriving logic functions of asynchronous circuits

    Publication Year: 1996 , Page(s): 30 - 35
    Cited by:  Papers (4)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (492 KB)  

    Signal Transition Graphs (STGs) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STGs some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCNs can represent both causality and concurrency between two nodes by ... View full abstract»

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  • General conditions for the decomposition of state holding elements

    Publication Year: 1996 , Page(s): 48 - 57
    Cited by:  Papers (22)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (684 KB)  

    A fundamental problem in the design of speed-independent asynchronous circuits is the decomposition or splitting up of high-fanin operators into two or more lower-fanin operators. In this paper, we develop general techniques to decided whether a particular decomposition of an arbitrary state-holding or combinational element into two elements with an belated internal signal is correct. These techni... View full abstract»

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  • Dynamic logic in four-phase micropipelines

    Publication Year: 1996 , Page(s): 11 - 16
    Cited by:  Papers (27)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (460 KB)  

    Micropipelines are self-timed pipelines with characteristics that suggest they may be applicable to low-power circuits. They were originally designed with two-phase control, but four-phase control appears to offer benefits for CMOS implementations. In low-power applications static circuit behaviour is desirable since it allows activity to cease (and hence power to be saved) without loss of state. ... View full abstract»

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  • Optimizing average-case delay in technology mapping of burst-mode circuits

    Publication Year: 1996 , Page(s): 244 - 260
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1584 KB)  

    This paper presents technology mapping techniques that optimize for average case delay of asynchronous burst-mode control circuits. First, the specification of the circuit is analyzed using stochastic techniques to determine the relative frequency of occurrence of each state transition. Then, subject to timing and area constraints, the technology mapper minimizes the sum of the cycle times of the ... View full abstract»

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  • Complete state encoding based on the theory of regions

    Publication Year: 1996 , Page(s): 36 - 47
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1192 KB)  

    Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which happens when a pair of different states in an SG has the same binary encoding. A standard way to approach state coding conflicts is to add new state signals into the original spe... View full abstract»

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  • Fred: an architecture for a self-timed decoupled computer

    Publication Year: 1996 , Page(s): 60 - 68
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (780 KB)  

    Decoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred is a self-timed decoupled, pipelined computer architecture based on micropipelines. We present the a... View full abstract»

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  • Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits

    Publication Year: 1996 , Page(s): 134 - 142
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (712 KB)  

    We present a pulse-driven asynchronous logic gate family based on a high-speed, low-power Josephson-junction device of rapid single-flux-quantum (RSFQ) circuits. Dual-rail logic is used and clock-free operation is realized. The proper operation of the circuits is confirmed by the numerical simulation which shows logic delays are about 60 ps for an AND and about 80 ps for an XOR. Power consumption ... View full abstract»

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  • Dynamic hazards and speed independent delay model

    Publication Year: 1996 , Page(s): 94 - 103
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (764 KB)  

    Different types of hazards have been studied extensively under the bounded gate and wire delay model. It is well known that under this delay model not all multiple input dynamic logic hazards can be removed from all two stage combinational logic circuits. In this paper we restrict the delay model to the well-known inertial gate delay or speed independent model and show that under this model half o... View full abstract»

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  • On the correctness of the Sproull counterflow pipeline processor

    Publication Year: 1996 , Page(s): 112 - 120
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (748 KB)  

    The Sproull Counterflow Pipeline Processor Architecture has been posed as a common problem in asynchronous design, so as to compare various design methodologies with one another. Using DI-algebra we discuss a path to a decomposition of the problem, which is subsequently shown to be correct. In the process we discover several design decisions that may have an impact on the performance of such a pip... View full abstract»

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  • Characterizing metastability

    Publication Year: 1996 , Page(s): 175 - 184
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (900 KB)  

    Determining metastability characteristics is challenging. Devising reliable and repeatable experiments and procedures requires time, patience, care and knowledge. This discussion presents practical measurement techniques to accurately determine the Resolving Time Constant (τ) and Metastability Window (W). Also included is a method for observing the metastability failure rate at a designated ti... View full abstract»

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  • A system for asynchronous high-speed chip to chip communication

    Publication Year: 1996 , Page(s): 2 - 10
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (784 KB)  

    A system for high-speed asynchronous interconnections between VLSI chips is proposed. Communication is performed on three-wire links that have about the same properties as differential interconnections. A bit transmission consists of switching the constant driver current from one wire to one of the two others. There is no need for clocking or synchronisation, as bits are separated by a transition.... View full abstract»

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  • The AMULET2e cache system

    Publication Year: 1996 , Page(s): 208 - 217
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (852 KB)  

    AMULET2e is an asynchronous microprocessor system based on the AMULET2 processor core. In addition to the processor it incorporates a number of distinct subsystems, the most notable of which is an asynchronous on-chip cache. This includes several novel features which exploit the asynchronous design style to increase throughput and reduce power consumption. These features are evident at a number of... View full abstract»

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  • Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits

    Publication Year: 1996 , Page(s): 222 - 232
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (856 KB)  

    This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic components previously implemented by skilled designers. However, the generality of the approach often involves the insertion of redundant functionality to the circuit. We propose a... View full abstract»

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  • Single-track handshake signaling with application to micropipelines and handshake circuits

    Publication Year: 1996 , Page(s): 122 - 133
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1036 KB)  

    Single-track handshake signaling is using the same wire for request and acknowledge signaling. After each 2-phase handshake the wire is back in its initial state. A sequence of three protocol definitions suggests both a design method for single-track circuits and a trade-off between their robustness and their cost/performance. Single-track handshake signaling is applied to micropipelines and to ha... View full abstract»

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  • Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems

    Publication Year: 1996 , Page(s): 164 - 174
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (792 KB)  

    We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The to... View full abstract»

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  • High-performance asynchronous pipeline circuits

    Publication Year: 1996 , Page(s): 17 - 28
    Cited by:  Papers (30)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1084 KB)  

    This paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The first circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for data storage in place of traditional transmission gate latches or Sutherland's capture-pass latches. The second circuit is a four-phase micropipeline with burst-... View full abstract»

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  • Static scheduling of instructions on micronet-based asynchronous processors

    Publication Year: 1996 , Page(s): 80 - 91
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (928 KB)  

    This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-specific heuristics. Their performance on some program graphs are presented and concl... View full abstract»

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  • Counterflow pipeline based dynamic instruction scheduling

    Publication Year: 1996 , Page(s): 69 - 79
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (848 KB)  

    This paper proposes a new dynamic instruction scheduler called the Asynchronous Fast Dispatch Stack (AFDS). This approach utilizes asynchronous design techniques to implement a dispatch stack-based dynamic instruction issue mechanism. To maintain throughput and simplify dependency computations, the AFDS architecture includes a counterflow pipeline, which is modeled after the Counterflow Pipeline P... View full abstract»

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  • Using partial orders for trace theoretic verification of asynchronous circuits

    Publication Year: 1996 , Page(s): 152 - 163
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (940 KB)  

    In this paper, we propose a method to generate the reduced state spaces in which the trace theoretic verification method of asynchronous circuits works correctly and efficiently. The state space reduction is based on the stubborn set method and similar ideas, but they have been extended so that the conformance checking works correctly in the reduced state space. Our state reduction algorithm also ... View full abstract»

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