IEE Colloquium on Hardware Accelerators for VLSI CAD - A Tutorial

5-5 Sept. 1988

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  • An overview of CAD acceleration

    Publication Year: 1988, Page(s):1/1 - 111
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (317 KB)

    The computational effort required in the application of CAD tools for VLSI design has meant that the use of hardware to reduce the increasingly large CPU times is widespread-indeed the use of hardware accelerators in VLSI design to speed-up the compute intensive aspects of CAD has been available now for several years. Many different machines from a large number of vendors can be purchased for task... View full abstract»

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  • Accelerating ATG and fault simulation

    Publication Year: 1988, Page(s):2/1 - 2/5
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (173 KB)

    Zycad have provided high performance tools to the simulation market now for several years. A recent addition to the product range is NextGen II which builds on Zycad's experience in logic and fault simulation to encompass the thorny sphere of Automatic Test Pattern Generation (ATPG). Within this paper the author discusses the growing need for Fault Simulation, particularly its relevance to AQL (Ac... View full abstract»

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  • Are hardware accelerators viable? The Manchester routing engine-a case study

    Publication Year: 1988, Page(s):3/1 - 3/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (176 KB)

    The increasing complexity of CAD tasks, coupled with the historical inadequacy of conventional computer resources, has led to the production of hardware accelerators for specific aspects of the design process. Recently, some opinion has questioned the viability of this approach because of the unrelenting increase in performance of general purpose computers, both conventional and parallel multiproc... View full abstract»

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  • A solution to high performance acceleration of digital system design

    Publication Year: 1988, Page(s):4/1 - 4/9
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (359 KB)

    Describes a hardware simulation accelerator that has been designed to handle components of extreme complexity (such as microprocessors) as well as incorporating advanced architectures to provide maximum simulation speed for low level primitives (e.g. ASICS). The issue of mixed-level component modelling for system design is considered first, and then the architecture of the accelerator, known as th... View full abstract»

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  • IEE Colloquium on 'Hardware Accelerators for VLSI CAD - A Tutorial' (Digest No.96)

    Publication Year: 1988
    IEEE is not the copyright holder of this material | PDF file iconPDF (18 KB)
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