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25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

12-15 June 1988

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Displaying Results 1 - 25 of 101
  • 25th ACM/IEEE Design Automation Conference. Proceedings 1988 (Cat. No.88CH2540-3)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • An automated BIST approach for general sequential logic synthesis

    Publication Year: 1988, Page(s):3 - 8
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (510 KB)

    An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through... View full abstract»

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  • Automatic insertion of BIST hardware using VHDL

    Publication Year: 1988, Page(s):9 - 15
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (519 KB)

    A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion ... View full abstract»

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  • VLSI design synthesis with testability

    Publication Year: 1988, Page(s):16 - 21
    Cited by:  Papers (25)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (530 KB)

    A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom-up and top-down tree algorithms provide datapath allocation, constraint estimation, and feedback for design e... View full abstract»

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  • A defect-tolerant and fully testable PLA

    Publication Year: 1988, Page(s):22 - 27
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (533 KB)

    The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this t... View full abstract»

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  • Experience with the VHDL environment

    Publication Year: 1988, Page(s):28 - 33
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (445 KB)

    The authors present their work in the use of the VHDL (VHSIC Hardware Development Language) environment on three different models of DEC VAX (1, 4, and 5.8 Mips (million instruction per second)). The work included the development of a number of VHDL models and sequences of input stimuli and the gathering of performance data from their execution. Even though the set of benchmarks is not in any way ... View full abstract»

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  • The role of VHDL in the MCC CAD system

    Publication Year: 1988, Page(s):34 - 39
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    A description is given of a suite of utilities for manipulating VHDL (VHSIC Hardware Description Language) designs that has been developed and integrated into a CAD (Computer-aided design) system. The system is a tightly integrated environment supporting the sharing of design information between heterogeneous tools, using an underlying knowledge base built on top of an object-orientated distribute... View full abstract»

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  • VHDL: a call for standards

    Publication Year: 1988, Page(s):40 - 47
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (454 KB)

    VHDL (VHSIC Hardware Description Language) is such an extremely flexible and versatile language, that the language reference documentation is not sufficient to ensure that models written by one hardware designer will be compatible with another's models. What is required is a set of VHDL modeling conventions and standard packages which structure the usage of VHDL modeling approaches. The issues inh... View full abstract»

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  • Verification of VHDL designs using VAL

    Publication Year: 1988, Page(s):48 - 53
    Cited by:  Papers (10)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB)

    VAL (VHDL Annotation Language) uses a small number of language constructs to annotate VHDL (VHSIC Hardware Description Language) hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. The result is a simple but expressive language extension of VHDL with possible applica... View full abstract»

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  • A module area estimator for VLSI layout

    Publication Year: 1988, Page(s):54 - 59
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.<<ET... View full abstract»

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  • A new area and shape function estimation technique for VLSI layouts

    Publication Year: 1988, Page(s):60 - 65
    Cited by:  Papers (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (494 KB)

    Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. A model is presented for the prediction of shape functions for aspect ra... View full abstract»

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  • Optimal aspect ratios of building blocks in VLSI

    Publication Year: 1988, Page(s):66 - 71
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (511 KB)

    A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which pr... View full abstract»

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  • Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

    Publication Year: 1988, Page(s):73 - 80
    Cited by:  Papers (53)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    The algorithms and the implementation of a novel macro/custom cell chip-planning, placement, and global routing package are presented. The simulated-annealing-based placement algorithm proceeds in two stages. In the first stage, the area around the individual cells is determined using novel interconnect area estimator. The second stage consists of: (1) a channel definition step, using a novel chan... View full abstract»

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  • Opportunities in computer integrated manufacturing

    Publication Year: 1988, Page(s):82 - 83
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The author argues that improved computer-integrated manufacturing (CIM) systems are needed to enable competitive production of high-technology products. The increasing complexity of processes and products, the growing need to manufacture different products in a single (costly) factory, and the rapid rate of change in product and process technologies all are trends that create a demand for better u... View full abstract»

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  • CONTEST: a concurrent test generator for sequential circuits

    Publication Year: 1988, Page(s):84 - 89
    Cited by:  Papers (60)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (523 KB)

    The application of a concurrent fault simulator to automatic test vector generation is described. As faults are simulated in the fault simulator, a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is fou... View full abstract»

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  • A method of delay fault test generation

    Publication Year: 1988, Page(s):90 - 95
    Cited by:  Papers (55)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (574 KB)

    The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. They define a type of transition path, the fully transitional path (FTP), and demonstrate that it has... View full abstract»

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  • SPLIT circuit model for test generation

    Publication Year: 1988, Page(s):96 - 101
    Cited by:  Papers (42)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (418 KB)

    A novel circuit model, SPLIT, is presented which is a modified 9-valued circuit model. SPLIT has the precision of the 9-valued model and the simplicity of the 5-valued model. So that its D-algorithm has better performance than that of the 5-valued or the 9-valued model.<<ETX>> View full abstract»

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  • A notation for describing multiple views of VLSI circuits

    Publication Year: 1988, Page(s):102 - 107
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (433 KB)

    A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basic of a structured environment for developing design generators as well as capturing design expertise.<<ETX>>... View full abstract»

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  • A graphical hardware design language

    Publication Year: 1988, Page(s):108 - 114
    Cited by:  Papers (4)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (562 KB)

    Gdl is a graphical hardware design language that separates design decisions into three interrelated but distinct domains: behavioral, structural, and physical. Specific language features are provided to represent a design in each of these domains. The process model for Gdl is described. Functional behavior is separated into distinct activities called 'processes' (autonomous control centers). The c... View full abstract»

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  • A human machine interface for silicon compilation

    Publication Year: 1988, Page(s):115 - 120
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (366 KB)

    A description is given of a novel human-machine interface for use as a design environment for silicon compilation. It is important for a human machine interface to support a tool which realizes quick turn around time with little possibility of user errors. Designers should be able to work with little interference with their thinking process. To realize such a design environment, the authors have d... View full abstract»

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  • Parallel placement on reduced array architecture

    Publication Year: 1988, Page(s):121 - 127
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The authors present a hardware accelerator for a module placement algorithm based on the divide-and-conquer paradigm. They consider a partitioning algorithm for the approximate solution of a large placement problem. This algorithm divides the set of logic modules into small clusters and generates an optimal placement for each cluster. Finally, in a pasting step, the algorithm combines the optimal ... View full abstract»

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  • Parallel channel routing

    Publication Year: 1988, Page(s):128 - 133
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB)

    A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing ... View full abstract»

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  • Mask verification on the Connection Machine

    Publication Year: 1988, Page(s):134 - 140
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (731 KB)

    Parallel mask verification algorithms have been developed for the Connection Machine, a massively parallel processor with up to 64K processors. A discussion is presented of the design and implementation of algorithms for several essential primitives: generation of completely intersected mask data, mask-to-mask Boolean operations, labeling of connected regions, and identification of width and spaci... View full abstract»

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  • On path selection in combinational logic circuits

    Publication Year: 1988, Page(s):142 - 147
    Cited by:  Papers (76)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate c... View full abstract»

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  • Pearl: a CMOS timing analyzer

    Publication Year: 1988, Page(s):148 - 153
    Cited by:  Papers (27)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (573 KB)

    Pearl is a timing analyzer that has been used to verify both full-custom VLSI and gate array designs. Rather than verify that a design meets a given clock timing, Pearl automatically determines the minimum error-free clock period and duty cycles. The author describes the mechanism used to determine the timing relationship each node in the circuit has with respect to the clock edges. He then shows ... View full abstract»

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