# IEEE Transactions on Electron Devices

## Issue 7 • July 2018

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## Filter Results

Displaying Results 1 - 25 of 67

Publication Year: 2018, Page(s):C1 - 2679
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2018, Page(s): C2
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• ### Changes to the Editorial Board

Publication Year: 2018, Page(s):2680 - 2681
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• ### Design and Comparative Analysis of Spintronic Memories Based on Current and Voltage Driven Switching

Publication Year: 2018, Page(s):2682 - 2693
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Spin transfer torque (STT)-based switching of magnetic random access memories (MRAMs) has stimulated considerable research interest in recent years. The nonvolatility of STT-MRAMs, high areal density, and low static power dissipation makes them a strong contender for possible replacement of conventional silicon-based memories. However, a major bottleneck associated with STT-MRAMs is their high wri... View full abstract»

• ### Charge-based Model for Junction FETs

Publication Year: 2018, Page(s):2694 - 2698
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We present a unified charge-based model for double-gate and cylindrical architectures of junction field-effect transistors (JFETs). The central concept is to consider the JFET as a junctionless FET (JLFET) with an infinitely thin insulating layer, leading to analytical expressions between charge densities, current, and voltages without any fitting parameters. Assessment of the model with numerical... View full abstract»

• ### Impact of Gaussian Doping Profile and Negative Capacitance Effect on Double-Gate Junctionless Transistors (DGJLTs)

Publication Year: 2018, Page(s):2699 - 2706
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In this paper, we study the impact of vertical Gaussian doping (GD) profile and ferroelectric (FE) negative capacitance phenomenon on the performance of nanoscale double-gate junctionless (JL) transistor. The device characteristics have been obtained by using the baseline approach of combining Landau–Khalatnikov equation with TCAD simulations. Doped HfO2 has been incorporated as ... View full abstract»

• ### Investigation of the Universal Mobility of SiC MOSFETs Using Wet Oxide Insulators on Carbon Face With Low Interface State Density

Publication Year: 2018, Page(s):2707 - 2713
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The universal mobility of SiC MOSFETs has been investigated. SiC MOSFETs with the gate oxide formed by wet oxidation have been fabricated on 4H-SiC ( $000overline {textsf {1}}$ ) substrates to reduce Coulomb scattering sources. In order to suppress charge trapping in the gate oxide during measurement, surface carrier concentrat... View full abstract»

• ### Embedding Statistical Variability Into Propagation Delay Time Compact Models Using Different Parameter Sets: A Comparative Study in 35-nm Technology

Publication Year: 2018, Page(s):2714 - 2720
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With shrinking transistor dimensions into sub-50-nm regime, statistical variability (SV) causes a great impact on the drain current and threshold voltage of nano-MOSFETs. In this paper, with emphasis on the propagation delay time of an inverter in 35-nm technology node, we have first introduced a strategy to take SV into account in four existing compact models using different number of statistical... View full abstract»

• ### Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si n-FinFET Performance

Publication Year: 2018, Page(s):2721 - 2728
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Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact resistances are strongly influenced by both the ambient temperature and within device lattice temperature. The ambient heat energy coupling through t... View full abstract»

• ### Quantitative Characterization of Fast-Trap Behaviors in Al2O3/GeOx/Ge pMOSFETs

Publication Year: 2018, Page(s):2729 - 2735
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In this paper, fast trap behaviors in Ge pMOSFETs with Al2O3/GeOx/Ge gate-stack are evaluated and quantitatively characterized using a novel sub-1-ns ultrafast measurement (UFM) system. By changing the operation temperature and the rising time of the applied gate voltage ( ${V}_{text {g}}$ View full abstract»

• ### Dirac Electrons at the Source: Breaking the 60-mV/Decade Switching Limit

Publication Year: 2018, Page(s):2736 - 2743
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Power consumption of today’s integrated circuit is very difficult to reduce because the MOSFET is subjected to the thermal limit of 60 mV/decade for the subthreshold swing (SS). In this paper, we show that this SS limit of thermionic current can be conquered—thus power consumption drastically reduced by density of states (DOS) engineering at the source. Specifically, the linear DOS o... View full abstract»

• ### Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part I: Drain Current and Transconductances

Publication Year: 2018, Page(s):2744 - 2750
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The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. ... View full abstract»

• ### Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part II: Total Charges and Transcapacitances

Publication Year: 2018, Page(s):2751 - 2756
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A compact model for the dynamic operation of double-gate junction field-effect transistors is established in this paper. Analytical model expressions are developed for the total node charges and transcapacitances valid from subthreshold to above threshold and from linear to saturation operation. The model is shown to conserve symmetry among source and drain, and circumvents problems at zero drain-... View full abstract»

• ### An Analytical Investigation on the Charge Distribution and Gate Control in the Normally-Off GaN Double-Channel MOS-HEMT

Publication Year: 2018, Page(s):2757 - 2764
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A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL ... View full abstract»

• ### Impact of Substrate Resistivity on the Vertical Leakage, Breakdown, and Trapping in GaN-on-Si E-Mode HEMTs

Publication Year: 2018, Page(s):2765 - 2770
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This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results d... View full abstract»

• ### Impacts of Finger Numbers on ON-State Characteristics in Multifinger SiC BJTs With Low Base Spreading Resistance

Publication Year: 2018, Page(s):2771 - 2777
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Impacts of finger numbers on ON-state characteristics in multifinger 10-kV-class SiC bipolar junction transistors (BJTs), whose base spreading resistance is sufficiently reduced by using aluminum ion implantation, were investigated by performing TCAD simulations. Common-emitter current–voltage characteristics of the BJTs with different base current densities and carrier lifetimes in the col... View full abstract»

• ### Degradation Mechanisms of GaN HEMTs With p-Type Gate Under Forward Gate Bias Overstress

Publication Year: 2018, Page(s):2778 - 2783
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This paper investigates the degradation of GaN-based HEMTs with p-type gate submitted to positive gate bias stress. Based on combined electrical and optical testing, we demonstrate the existence of different degradation processes, depending on the applied stress voltage ${V}_{textsf {Gstress}}$ : 1) for View full abstract»

• ### The Physical Mechanisms Behind the Strain-Induced Electron Mobility Increase in InGaAs-On-InP MOSFETs

Publication Year: 2018, Page(s):2784 - 2789
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The electron mobility in strained ultra-thin InGaAs-on-InP MOSFETs is investigated combining band-structure and physics-based modeling including all relevant scattering mechanisms and effects. The most important effect is Fermi-level pinning which occurs due to high density of interface states at InGaAs/oxide interface. Different interface states densities are considered in order to investigate im... View full abstract»

• ### Vertical Geometry, 2-A Forward Current Ga2O3 Schottky Rectifiers on Bulk Ga2O3 Substrates

Publication Year: 2018, Page(s):2790 - 2796
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Large area (up to 0.2 cm2) Ga2O3 rectifiers without edge termination were fabricated on a Si-doped n-Ga2O3 drift layer grown by halide vapor phase epitaxy on a Sn-doped n+Ga2O3 (001) substrate. A forward current of 2.2 A was achieved in single-sweep voltage mode, a record for Ga2O3 ... View full abstract»

• ### High Retention With ${n}$ -Oxide- ${p}$ Junctionless Architecture for 1T DRAM

Publication Year: 2018, Page(s):2797 - 2803
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This paper reports on the potential benefits of a vertically stacked ${n}$ - and ${p}$ -type junctionless (JL) transistor physically decoupled through an intermediate oxide layer for dynamic memory application. The proposed topology enhances the retention ... View full abstract»

• ### Investigation and Compact Modeling of the Time Dynamics of the GIDL-Assisted Increase of the String Potential in 3-D NAND Flash Arrays

Publication Year: 2018, Page(s):2804 - 2811
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This paper presents a detailed analysis of the time dynamics of the gate-induced drain leakage (GIDL)-assisted increase of the string potential in vertical-channel 3-D NAND Flash arrays. The string potential and the GIDL current waveforms are first studied with close attention by means of technology computer-aided design simulations, highlighting the major phases of their time evolution. A compact... View full abstract»

• ### Abnormal Volatile Memory Characteristic in Normal Nonvolatile ZnSnO Resistive Switching Memory

Publication Year: 2018, Page(s):2812 - 2819
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Resistive random access memory is known as a type of nonvolatile memory. An abnormal volatile memory characteristic of a normal ZnSnO resistive memory is first demonstrated in this paper. Although the ${I}$ – ${V}$ curves exhibit a normal and stable... View full abstract»

• ### A Bottom-Gate Metal–Oxide Thin-Film Transistor With Self-Aligned Source/Drain Regions

Publication Year: 2018, Page(s):2820 - 2826
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Proper driving of a large-area, high-resolution, and high-frame-rate active-matrix display can be hindered by excessive delay along a signal path, such as a scan line. Depending on the transistor architecture, such delay could be dominated by the parasitic overlap capacitance between the gate electrodes and the source/drain (S/D) regions of the address-transistors attached to a scan line. While th... View full abstract»

• ### Fabrication of Amorphous Indium–Gallium– Zinc–Oxide Thin-Film Transistor on Flexible Substrate Using a Polymer Electrolyte as Gate Dielectric

Publication Year: 2018, Page(s):2827 - 2832
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We have fabricated a flexible thin-film transistor (TFT) with relevant high performance indices using polymer electrolyte as gate dielectric and amorphous indium–gallium–zinc–oxide (a-IGZO) (a-InGaZn2O5) as a channel on polyimide Kapton tape. Low temperature ( $approx 100~^{circ }text{C}$ View full abstract»

• ### Effect of High Oxygen Partial Pressure on Carrier Transport Mechanism in a-InGaZnO TFTs

Publication Year: 2018, Page(s):2833 - 2837
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In this paper, the influence of oxygen partial pressure ( ${P}_{textsf {O2}}$ ) during physical vapor deposition on the field-effect mobility of amorphous InGaZnO (IGZO) thin-film transistor (TFT) is investigated in a wide range of ${P}_{textsf {O2}}$ . The... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy