# IEEE Transactions on Electron Devices

## Issue 4 • April 2019

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## Filter Results

Displaying Results 1 - 25 of 75

Publication Year: 2019, Page(s):C1 - 1627
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2019, Page(s): C2
| PDF (134 KB)
• ### Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application

Publication Year: 2019, Page(s):1628 - 1634
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In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel field-effect transistor (TFET). The proposed device employs a lateral dual source with a vertical drain extension on top of T-shaped channel region. This enables the modification of screening length ( $\lambda$ ) by varying the... View full abstract»

• ### Impact of Punch-through Stop Implants on Channel Doping and Junction Leakage for Ge ${p}$ -FinFET Applications

Publication Year: 2019, Page(s):1635 - 1641
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Fin field-effect transistor (FinFET) scaling beyond the 10-nm node requires formation of a junction isolation region between the source and the drain to suppress sub-fin leakage current. In this paper, heavy species such as Sb and As were implanted at room temperature to form a punch-through stop (PTS) layer in ${n}$ -Ge subst... View full abstract»

• ### Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode

Publication Year: 2019, Page(s):1642 - 1647
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We demonstrate a gate-lifted nMOS electrostatic discharge (ESD) protection device triggered by a p-n-p in series with a diode in a 0.18- $\mu \text{m}$ bulk CMOS technology for 5-V mobile applications up to 85 °C. This voltage-triggering scheme is suitable for fail-safe, open-drain, supply, and surge protections. In addition, ... View full abstract»

• ### Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

Publication Year: 2019, Page(s):1648 - 1655
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A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equi... View full abstract»

• ### Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

Publication Year: 2019, Page(s):1656 - 1661
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This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current (<... View full abstract»

• ### NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

Publication Year: 2019, Page(s):1662 - 1668
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We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NBTI measurements and an extensive TCAD analysis, we study two physics-based compact models for analog-stress NBTI including recovery. The high accuracy... View full abstract»

• ### Experimental Investigation of Remote Coulomb Scattering on Mobility Degradation of Ge pMOSFET by Various PDA Ambiences

Publication Year: 2019, Page(s):1669 - 1674
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The impact of various postdeposition annealing (PDA) ambiences (N2, O2, and NH3) on the hole mobility of germanium (Ge) pMOSFET with GeO2/Al2O3 gate-stack is investigated. It is found that the mobility is about 10% higher after N2 PDA, while it is about 10% smaller after O2 and NH3 PDA than that with... View full abstract»

• ### The Role of Near-Interface Traps in Modulating the Barrier Height of SiC Schottky Diodes

Publication Year: 2019, Page(s):1675 - 1680
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The role of traps in the operation of Schottky barrier diodes is poorly understood. To explore this, SiC Schottky barrier diodes with a high density of near-interface traps were intentionally fabricated. By applying forward current stress, we demonstrate that the barrier height can be changed by changing the occupancy of the traps. The response time of these traps extends from seconds to hundreds ... View full abstract»

• ### Quantifying Temperature-Dependent Substrate Loss in GaN-on-Si RF Technology

Publication Year: 2019, Page(s):1681 - 1687
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Intrinsic limits to temperature-dependent substrate loss for GaN-on-Si technology, due to the change in resistivity of the substrate with temperature, are evaluated using an experimentally validated device simulation framework. Effect of room temperature substrate resistivity on temperature-dependent coplanar waveguide (CPW) line loss at various operating frequency bands is then presented. CPW lin... View full abstract»

• ### Field Plate Designs in All-GaN Cascode Heterojunction Field-Effect Transistors

Publication Year: 2019, Page(s):1688 - 1693
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Different source field plate (FP) connections are compared for the all-GaN integrated cascode device to address the capacitance matching and turn-off controllability issues reported in the conventional GaN plus Si cascode. The experimental results suggest that the cascode device with an FP connected to the source terminal can significantly suppress the off-state internode voltage, leading to minim... View full abstract»

• ### Electrical Characteristic of AlGaN/GaN High-Electron-Mobility Transistors With Recess Gate Structure

Publication Year: 2019, Page(s):1694 - 1698
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AlGaN/GaN high-electron-mobility transistors (HEMTs) with nonrecess and recess gates are simulated by solving a set of drift–diffusion equations for electrostatic potential and electron–hole concentrations with self-heating model. The approach is first calibrated for both HEMT devices with experimentally measured data, to provide the best accuracy of the simulation. Recess gate device suffers from... View full abstract»

• ### Deep Sub-60 mV/decade Subthreshold Swing in AlGaN/GaN FinMISHFETs with M-Plane Sidewall Channel

Publication Year: 2019, Page(s):1699 - 1703
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AlGaN/GaN FinMISHFETs with m-plane sidewall surface channel and various fin widths ( $\text{W}_{\textsf {fin}}$ ) were fabricated and characterized. The investigated devices have much higher current drivability due to the uniform and smooth surface of m-plane than those with the a-plane sidewall surface channel. The AlGaN/GaN F... View full abstract»

• ### Energy-Localized Near-Interface Traps Active in the Strong-Accumulation Region of 4H-SiC MOS Capacitors

Publication Year: 2019, Page(s):1704 - 1709
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Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above th... View full abstract»

• ### Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate-Stack

Publication Year: 2019, Page(s):1710 - 1716
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High-performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm2/ $\text{V}\,\cdot$ s, and a peak field effect mobility of 154 cm2/V s, in 2- $\mu$ m gate length MOSFETs. The gate-stack was designed ... View full abstract»

• ### Enhanced Reconfigurable Physical Unclonable Function Based on Stochastic Nature of Multilevel Cell RRAM

Publication Year: 2019, Page(s):1717 - 1721
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The physical unclonable function (PUF) based on resistive random-access memory (RRAM) possesses a distinctive advantage that can offer higher security and lower cost than the traditional complementary metal–oxide–semiconductor-based cryptographic devices and other conventional PUFs. The intrinsic stochasticity of RRAM devices successfully provides attractive properties to implement PUF. In this pa... View full abstract»

• ### Adaptive Quantization as a Device-Algorithm Co-Design Approach to Improve the Performance of In-Memory Unsupervised Learning With SNNs

Publication Year: 2019, Page(s):1722 - 1728
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Off-chip memory access is the primary bottleneck toward accelerating neural network operations and reducing energy consumption. In-memory training and computation using emerging nonvolatile memories (eNVMs) have been proposed to address this problem. However, a small number of conductance states limit in-memory online learning performance. Here, we introduce a device-algorithm co-design approach a... View full abstract»

• ### Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process

Publication Year: 2019, Page(s):1729 - 1733
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A new antifuse one-time programmable (OTP) memory array by the 16-nm FinFET high- $\pmb \kappa$ metal gate process is proposed and demonstrated. The OTP cells are programed by gate dielectric breakdown. The asymmetric ${I}$ – View full abstract»

• ### Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String

Publication Year: 2019, Page(s):1734 - 1740
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Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of $10~\mu \text{s}$ or longer and is strongly dependent on the bias history. It is also affec... View full abstract»

• ### Investigation of the Impact of External Stress on Memory Characteristics by Modifying the Backside of Substrate

Publication Year: 2019, Page(s):1741 - 1746
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The effects of the external stress on memory device characteristics are numerically discussed, and experimental observations are made, based on the wafer curvature method for extraction of stress. An analysis of the interface state is then performed. The external force applied to the device was controlled by depositing a metal film on the wafer backside; then, the residual stress induced on the su... View full abstract»

• ### Study on High-Density Integration Resistive Random Access Memory Array From Multiphysics Perspective by Parallel Computing

Publication Year: 2019, Page(s):1747 - 1753
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A finite-element method-based parallel computing simulator for multiphysics effects in resistive random access memory (RRAM) array, which is suitable for supercomputer platforms even with thousands of cores, is developed to simulate oxygen vacancy migration, current transport, and thermal conduction. Exponentially fit flux Galerkin method is introduced to improve algorithm convergence when solving... View full abstract»

• ### Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology

Publication Year: 2019, Page(s):1754 - 1759
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A scheme for precisely adjusting the drive strength of an inserted-oxide FinFET (iFinFET) comprising two nanowire (NW) channel regions that are separated by a thin oxide layer, to enhance the manufacturing yield of a minimally sized six-transistor static random access memory (6T-SRAM) cell, is investigated in this paper. The 3-D process simulations show that the upper NW channel region can be sele... View full abstract»

• ### Enhanced Stability in Zr-Doped ZnO TFTs With Minor Influence on Mobility by Atomic Layer Deposition

Publication Year: 2019, Page(s):1760 - 1765
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We developed a novel method to fabricate Zr-doped ZnO (ZrZnO) thin films via low-temperature atomic layer deposition technique. ZrZnO films were deposited by diethylzinc (DEZ)/tetrakiszirconium (TDMAZr)/H2O cycles instead of the traditional DEZ/H2O/TDMAZr/H2O cycles and applied in thin-film transistors (TFTs). It is found that ZrZnO-TFTs with a Zn-Zr-O:ZnO atomic r... View full abstract»

• ### Submicrometer p-Type SnO Thin-Film Transistors Fabricated by Film Profile Engineering Method

Publication Year: 2019, Page(s):1766 - 1771
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We reported the fabrication of submicrometer p-type tin monoxide (SnO) thin-film transistors (TFTs) with a channel length of $0.2~\mu \text{m}$ for back-end-of-line applications using a film profile engineering (FPE) approach. Material analyses indicate that the as-deposited SnO films are amorphous, while be transformed to po... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy