IEE Colloquium on Hardware Implementation of Neural Networks and Fuzzy Logic

1994

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  • A systolic array circuit for the fuzzy inference process

    Publication Year: 1994, Page(s):9/1 - 9/6
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (352 KB)

    The fuzzy inference process is mostly used in control applications today. Investigations show that for possible future application cases, for instance fuzzy expert systems and multi-stage controllers, sup-min composition in combination with Godel implication will achieve better results than the match factor method which is generally used in fuzzy hard- and software for cost reasons. This permits t... View full abstract»

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  • Novel analogue CMOS defuzzification circuit technique

    Publication Year: 1994, Page(s):8/1 - 8/3
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (156 KB)

    A novel analogue CMOS circuit technique for performing defuzzification is proposed, operating in current mode. This can thus be used in conjunction with existing current mode-based fuzzy processing circuits. The defuzzification method is based on the Normalisation Locked Loop (NLL) method, with improvements to allow the processing of triangular membership functions whilst ensuring that relative ru... View full abstract»

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  • A new class of analogue CMOS neural network circuits

    Publication Year: 1994, Page(s):7/1 - 7/3
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (191 KB)

    Presents analogue circuit techiques that provide area efficient implementation of the functions required in a neural network namely, multiplication, RC delay, charge storage and the sigmoid transfer characteristics.<<ETX>> View full abstract»

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  • A study of noise in PWM neural networks

    Publication Year: 1994, Page(s):6/1 - 6/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (211 KB)

    Shows the effect of introducing noise to the weight set and at the input to the neuron. The MLP investigated is tolerant to noise added at the input to the neuron and therefore could be implemented using the PWM neural network with the RC time constant set close to the PWM period.<<ETX>> View full abstract»

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  • An integrated neural network incorporating a novel synapse design

    Publication Year: 1994, Page(s):5/1 - 5/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (258 KB)

    A VLSI implementation of an Artificial Neural Network using a single n-channel MOS transistor per synapse is investigated. The simplicity of the design is achieved by using pulse width modulation to represent neural activity and a novel technique for manipulating synaptic weights. A multi layer perceptron network built in hardware gives good results for a simple classification task.<<ETX>... View full abstract»

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  • A family of VLSI neural processors for real-time applications

    Publication Year: 1994, Page(s):4/1 - 4/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (296 KB)

    The need for efficient, high-speed realisation of large-scale neural systems has led to the development of a wide variety of custom-designed electronic implementations covering the full range of processor architectures. An ANN system, HyperNet, based on a probabilistic, RAM-based, feed forward architecture and utilising a custom VLSI IC with on-board Reward-Penalty learning has been developed and ... View full abstract»

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  • Hardware implementation of Boolean neural networks

    Publication Year: 1994, Page(s):3/1 - 3/4
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (248 KB)

    Describes an approach for implementing Boolean Neural Networks on silicon. The hardware is based on a custom designed Field Programmable Logic Device (FPLD) which integrates 'synapses' and 'neurons' and allows random access to the weights during training. Networks are realised from arrays of the neural chip which are assembled on ceramic as Multi-Chip Modules (MCM) to provide expandability and fle... View full abstract»

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  • Field programmable gate array implementation of a neural network accelerator

    Publication Year: 1994, Page(s):2/1 - 2/3
    Cited by:  Papers (5)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (229 KB)

    The use of a neural network to learn the nonlinear current profiles required to minimise torque ripple in a switched reluctance motor (SRM), at low to medium speeds, has been demonstrated using a digital signal processor (DSP). However, the DSP (Texas Instruments TMS320C25) implementation of a neural network in this application is a limiting factor on motor speed (if maximum current profile integr... View full abstract»

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  • Implementing neural networks in FPGAs

    Publication Year: 1994, Page(s):1/1 - 1/5
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (347 KB)

    The reconfigurability of certain field programmable gate arrays (FPGAs) has shown their advantage of flexibility in digital system design. With the availability of greater density and high speed of FPGAs, the ability to realise special purpose processors will become possible. The authors present the research work of implementing specific trained neural network in Xilinx XC4000 series FPGAs for por... View full abstract»

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  • IEE Colloquium on 'Hardware Implementation of Neural Networks and Fuzzy Logic' (Digest No.1994/061)

    Publication Year: 1994
    IEEE is not the copyright holder of this material | PDF file iconPDF (198 KB)
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