2006 IEEE International Symposium on Circuits and Systems

21-24 May 2006

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  • 2006 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 06CH37717C)

    Publication Year: 2006
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  • [Breaker page]

    Publication Year: 2006, Page(s): 1
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  • [Breaker page]

    Publication Year: 2006, Page(s): 1
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  • Table of contents

    Publication Year: 2006, Page(s): iii
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  • [Commentary]

    Publication Year: 2006, Page(s): iv
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  • [Commentary]

    Publication Year: 2006, Page(s): v
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  • [Society related material]

    Publication Year: 2006, Page(s):vi - ix
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    Publication Year: 2006, Page(s):x - xi
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  • Contributor Listings

    Publication Year: 2006, Page(s):xii - xiii
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  • [Commentary]

    Publication Year: 2006, Page(s):xiv - xvi
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  • Tutorial

    Publication Year: 2006, Page(s): xvii
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    Provides an abstract of the presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Staff or Society listings

    Publication Year: 2006, Page(s): xviii
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    Publication Year: 2006, Page(s): xix
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    Publication Year: 2006, Page(s): xx
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    Publication Year: 2006, Page(s): xxi
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  • Digit-serial/parallel multipliers with improved throughput and latency

    Publication Year: 2006
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1353 KB) | HTML iconHTML

    Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long critical paths that are reduced by splitting the multiplication as a sum of partial multiplications. Using a sum of two partial multiplications yields an increased throughput with between 50 and 120 percent and the la... View full abstract»

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  • Multiplier reduction tree with logarithmic logic depth and regular connectivity

    Publication Year: 2006, Page(s):4 pp. - 8
    Cited by:  Papers (16)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    A novel partial-product reduction circuit for use in integer multiplication is presented. The high-performance multiplier (HPM) reduction tree has the ease of layout of a simple carry-save reduction array, but is in fact a high-speed low-power Dadda-style tree having a worst-case delay which depends on the logarithm (O(log TV)) of the word length N View full abstract»

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  • Implementation of a high-speed low-power 32-bit adder in 70nm technology

    Publication Year: 2006, Page(s):4 pp. - 12
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (2550 KB) | HTML iconHTML

    In this article, the performance and power dissipation of two differential logic circuits in deep sub-micron technologies are obtained and compared together, and the superior topology is introduced. Low voltage swing (LVS) technique which improves circuit performance and lowers power consumption is described in detail. We conclude this article with the design, simulation and optimization of a high... View full abstract»

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  • A 372 ps 64-bit adder using fast pull-up logic in 0.18-/spl mu/m CMOS

    Publication Year: 2006, Page(s):4 pp. - 16
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (4709 KB) | HTML iconHTML

    This paper presents a 372 ps 64-bit adder using fast pull-up logic (FPL) in 0.18 mum CMOS technology. Fast pull-up logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372 ps. The adder has a modified tree architecture using load distribution method and has 6 logic stages View full abstract»

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  • Low power binary addition using carry increment adders

    Publication Year: 2006, Page(s):4 pp. - 20
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (3885 KB) | HTML iconHTML

    Sparse prefix tree adders like carry-select adders and carry-increment adders are commonly used in the implementation of high-speed parallel adders. This paper presents a novel Ling carry-increment adder, which further reduces the area and power consumption as compared to a conventional carry-increment adder. The proposed algorithm utilizes Ling pseudo-carries in both the prefix tree and the outpu... View full abstract»

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  • Ultra-low voltage VLSI: are we there yet?

    Publication Year: 2006, Page(s):4 pp. - 24
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (2814 KB) | HTML iconHTML

    Aggressively scaled supply voltage has been touted as one of the most powerful mechanisms for improving reliability and reducing power consumption in nanometer technologies. Sophisticated adaptive power management techniques vary supply voltage from nominal to ultra-low values to implement adaptive VLSI systems that gracefully respond to varying workload demands for improved energy efficiency. Unf... View full abstract»

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  • Ultra-low voltage nano-scale embedded RAMs

    Publication Year: 2006, Page(s):4 pp. - 28
    Cited by:  Papers (2)
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    Ultra-low voltage nano-scale embedded RAMs are described, focusing on RAM cells and peripheral circuits. First, challenges and trends of low-voltage RAM cells are discussed in terms of signal charge, signal voltage, and noise. ECC to cope with the ever-increasing soft-error rate, power-supply controls to widen the voltage margin of cells, and a fully-depleted SOI to reduce V<sub>T</sub>... View full abstract»

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  • Energy efficient design for subthreshold supply voltage operation

    Publication Year: 2006, Page(s):4 pp. - 32
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (4194 KB) | HTML iconHTML

    Subthreshold design has become an important area in low-power design due to its ultra-low power consumption and high energy efficiency. This is very useful in mobile applications where battery life is crucial. For most current DVS processor designs, the voltage range is limited from full V<sub>dd</sub> to approximately half V<sub>dd </sub> at most. Subthreshold design enabl... View full abstract»

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  • Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits

    Publication Year: 2006, Page(s):4 pp. - 36
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (2432 KB) | HTML iconHTML

    Enabled by technology scaling, ultra low-voltage devices have now found wide application in modern VLSI circuits. While low-voltage implies reduced dynamic power, it also signifies increased leakage power, as lower supply voltages are usually paired with lower threshold voltages in order to preserve circuit speed. This originates an increase in sub-threshold leakage currents that constitute, today... View full abstract»

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  • Localized microarchitecture-level voltage management

    Publication Year: 2006, Page(s):4 pp. - 40
    Cited by:  Patents (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (3900 KB) | HTML iconHTML

    Diminishing voltage margins, coupled with power and temperature constraints, call for microarchitecture-level runtime mechanisms for voltage control. This paper describes a localized approach for dynamic voltage management within the domains of a globally asynchronous, locally synchronous (GALS) processor design. Dynamic voltage scaling at this fine grain level permits effective temperature manage... View full abstract»

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