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Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE

Date 22-24 May 2006

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Displaying Results 1 - 25 of 91
  • ASMC 2006 is produced and organized through the generous support of: [SEMI and IEEE]

    Publication Year: 2006 , Page(s): i
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    Freely Available from IEEE
  • 2006 ASMC Organizing Committee

    Publication Year: 2006 , Page(s): ii
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    Freely Available from IEEE
  • Applied Materials

    Publication Year: 2006 , Page(s): iii
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  • Table of contents

    Publication Year: 2006 , Page(s): iv - x
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  • Welcome to ASMC 2006

    Publication Year: 2006 , Page(s): xi
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  • Experimental Evaluation of Second Harmonic Generation for Non-Invasive Contamination Detection in SOI Wafers

    Publication Year: 2006 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (525 KB) |  | HTML iconHTML  

    We report experimental results from non-invasive second harmonic generation (SHG) measurements applied to detect the presence of contamination at the silicon/buried oxide (BOX) and BOX/substrate interfaces in silicon-on-insulator (SOI) wafers. The potential application of SHG as a metrology tool for process control is demonstrated View full abstract»

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  • The Development of the Non-contact Electrical Leakage Property Measurement System for the High-K Dielectric Materials on DRAM Capacitors

    Publication Year: 2006 , Page(s): 7 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    We have used the non-contact electrical property measurement system to characterize the electrical leakage property of high-K materials such as Al2O3 and HfO2 on a patterned wafer. The basic technology is to measure the surface voltage with micro Kelvin probe after the corona charge deposition on a measurement area. Because of the charge decay through a dielectric material, voltage-time spectra follow exponential time dependence that is the characteristic of leakage induced charge decay. We have measured the electrical leakage property of the storage capacitors on the direct cell area of DRAM device. The measured electrical leakage property can be classified according to the thickness of Al2O3 and HfO2. Since the electrical leakage property depends on a thickness of a dielectric material, voltage-time spectra show different shapes according to the HfO2 thickness. Using the technology, we can monitor the electrical leakage property of the storage capacitors of high-K materials on the direct cell area View full abstract»

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  • New methodology for ultra-fast detection and reduction of non-visual defects at the 90nm node and below using comprehensive e-test structure infrastructure and in-line DualBeamTM FIB

    Publication Year: 2006 , Page(s): 12 - 16
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB)  

    This paper describes a methodology to quickly capture, characterize, prioritize, localize, and perform in-line FA on killer defects. The system, which includes comprehensive short-flow test wafers, fast inline e-test, a powerful data analysis system, and advanced in-line dual beam inspection, was demonstrated in a leading-edge 300mm fab at the 90nm technology node to detect and resolve both systematic and random defect mechanisms greater than 10times faster than traditional methods. This article describes several examples of detecting and resolving non-visual (subsurface) as well as visual defects for both back-end and front-end issues View full abstract»

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  • Incorporating SIMS Structures in Product Wafers in Order to Perform SIMS and other Material Analysis and Achieve Wafer Level Information about the Front-End Processing

    Publication Year: 2006 , Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB) |  | HTML iconHTML  

    In this paper, we summarize how the introduction of SIMS structures near the global alignment marks of product wafers serve as an additional way to acquire detailed analytical information about front-end processing and can minimize product yield loss without waiting for metal 1 processing when electrical testing (ET) becomes possible View full abstract»

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  • Advanced Process Monitoring and Control Methods for Poly Gate CD Targeting

    Publication Year: 2006 , Page(s): 21 - 24
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1009 KB) |  | HTML iconHTML  

    Accurate poly critical dimension (CD) control is necessary to run speed-sensitive parts in high volume production. A source-of-variation study indicated that poly CD variation accounted for over 50% of end-of-line variation in speed and power for a critical production part. A team was established to implement process control methodologies to reduce poly CD variation. The team took a module-based approach - linking outputs from the lithography, etch, and implant areas to form the tightest possible control for optimal product performance View full abstract»

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  • Metal Layer Monitoring in DRAM Production by use of Spectroscopic Ellipsometry-based Scatterometry

    Publication Year: 2006 , Page(s): 25 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (750 KB) |  | HTML iconHTML  

    Current available metrology methods for metal layer line monitoring could include atomic force microscopic (AFM) scanning for trench depth measurement and top-down secondary electron microscope for CD measurement (CD-SEM). However, they both suffer from incomplete information outputs and repeatability issue. Transmission electron microscope (TEM) cross-sections and SEM cross-sections are the two major techniques for obtaining detailed profile information. However, both they are destructive and time-consuming. Scatterometry comes in as a potential process-monitoring candidate for the metal layer process. In this work, we use SE-based scatterometry to demonstrate a two-dimensional profile of the metal trench profile with post-etched structure, as well as CD and depth measurements of the trench. Theory and measurement results of dense structure are briefly discussed. These results are correlated to SEM cross-sections, AFM measurements and CD-SEM measurements. The data shows high correlation between them. Moreover, WAT data were seen a high correlation result in the paper as well View full abstract»

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  • Defectivity Performance of Full Field Immersion Photolithography Tool

    Publication Year: 2006 , Page(s): 30 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3954 KB) |  | HTML iconHTML  

    In this paper, we report results of comprehensive studies of defects originating in immersion photolithography clusters comprising immersion volume production tool (S609B, NA=1.07) and engineering evaluation tool (EET NA = 0.85). Defectivity S609B was very low, 0.013 cm2 it attained dry exposure level successfully. Defectivity results using EET were also very promising in all three major resist processes including solvent soluble topcoat, developer soluble topcoat and topcoat-less resist. Defectivity did not show any scan speed dependency and target size dependency, showing the extendibility of our immersion technology in future mass production phase. In particular, we found that for 50 ml water droplets, weeding angle larger than about 70 degree provides immersion process free of immersion-specific defects. We successfully demonstrated very effective defect analysis technique named DSA (defect source analysis) to show what defects are immersion-specific. We also revealed the defect generation mechanism of each defect types. Deep understanding of defectivity behavior leads to a conclusion that immersion lithography is viable for IC manufacture at 45 nm node View full abstract»

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  • High and Hyper NA Immersion Lithography using Advanced Patterning Film APF TM

    Publication Year: 2006 , Page(s): 39 - 43
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1053 KB) |  | HTML iconHTML  

    The objective of this work is to enable the manufacturing of features with most aggressive pitches available to date using APF as a strippable hard mask (HM). Essential for the capability of printing small and in particular dense features is the control of optical reflections during exposure. This is achieved through control of the optical parameters of the used films. The considered optical parameters are the complex reflection coefficient (ntilde = n - ik) and thickness. The angle of incidence of the exposing light when using high or hyper NA (numerical aperture) lithography is no longer negligible. As a consequence the optimum film thickness corresponding to the lowest reflection varies with the pitch of the features being imaged. In this paper we discuss the results based on a hyper-NA simulation illustrating the complexity of such an optimization process. Furthermore we discuss various high-NA simulations and corresponding physical experimental work confirming the validity of this approach View full abstract»

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  • Performance Evaluation of Serial Photolithography Clusters: Queueing Models, Throughput and Workload Sequencing

    Publication Year: 2006 , Page(s): 44 - 49
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (329 KB) |  | HTML iconHTML  

    For clustered configuration of a photolithography toolset, operating under a scheduling policy inducing serial processing, measures of system performance are deduced. Queueing models demonstrate that, due to the parallelism inherent in the system configuration, the normalized cycle time behavior is different than that of the standard single server queue. Cluster throughput is evaluated based on measures of the frequency and magnitude of events common in manufacturing operation. It is shown that the maximum throughput of a serial photolithography cluster tool is not influenced by the order in which two classes of lots with different wafer processing speeds are processed View full abstract»

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  • Performance of Polarized Illuminators in Hyper NA Lithography Tools

    Publication Year: 2006 , Page(s): 50 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2213 KB) |  | HTML iconHTML  

    Polarized light illumination is essential for hyper-NA imaging such as immersion lithography. This is confirmed by comparison of optical images between unpolarized light illumination condition and polarized light illumination condition. In this paper, we introduce our polarized light illumination apparatus and some experimental results, which confirm the effect of improvement of the imaging performance by utilization of polarized light illumination. In addition, required quality of the polarized light illumination for hyper NA lithography is discussed View full abstract»

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  • Robust Real-Time Thin Film Thickness Estimation

    Publication Year: 2006 , Page(s): 57 - 62
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB) |  | HTML iconHTML  

    The dissolution of photoresist in developer solution often leads to changes in the chemical composite of the solution which hinder film thickness estimation. This paper addresses this issue by proposing a modified fringe order computation (MFOC) method which analyses reflected light intensity data acquired using commercially available optical spectrometry system. MFOC uses simple arithmetic operations and is capable of computing film thickness at real-time. It is more reliable as compared to other methods during develop step in microlithography process View full abstract»

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  • Full Field, ArF Immersion Projection Tool

    Publication Year: 2006 , Page(s): 63 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    Immersion lithography is rapidly approaching the manufacturing phase. A production-quality exposure tool system with NA = 1.07 (Nikon NSR-S609B) was constructed to target the start of immersion lithography for IC manufacturing in 2006. Its projection optics has very small wave-front aberration and lowest local flare levels. The overlay issue has been analyzed, and its cause was found to be evaporation cooling. With the tandem stage and local fill nozzle implemented in the S609B, we have successfully avoided the evaporation cooling so that the good wet-to-dry mix-and-match overlay data have been obtained. The major part of immersion specific defects is caused by dried water-droplets, i.e. water-marks. The local fill nozzle has eliminated this defectivity by avoiding airflow in the nozzle. In the future, water immersion with NA = 1.30 optics will be used for half-pitch 45 nm manufacturing View full abstract»

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  • STI Gap-Fill Technology with High Aspect Ratio Process for 45nm CMOS and beyond

    Publication Year: 2006 , Page(s): 71 - 76
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (485 KB) |  | HTML iconHTML  

    In the present work the high aspect ratio process (HARP) using a new O3/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gap fill in sub-65nm CMOS. We prove good gap fill performance up to aspect ratios larger 10:1. Since this fill process doesn't attack the STI liners as compared to HDP, a variety of different STI liners can be implemented View full abstract»

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  • Pattern Based Prediction for Plasma Etch

    Publication Year: 2006 , Page(s): 77 - 82
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    Plasma etching is a key process for pattern formation in integrated circuit (IC) manufacturing. Unfortunately, pattern dependent non-uniformities arise in plasma etching processes due to microloading and RIE lag. We contribute a semi-empirical methodology for capturing and modeling pattern dependent effects in plasma etching of ICs. We apply this methodology to the study of interconnect trench etching, and show that an integrated model is able to predict both pattern density and feature size dependent non-uniformities in trench depth View full abstract»

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  • Control of Contact Hole Distortion by Using Polymer Deposition Process (PDP) for sub-65nm Technology and Beyond

    Publication Year: 2006 , Page(s): 83 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (705 KB) |  | HTML iconHTML  

    Contact hole distortion in dielectric etching was investigated and it is found that the contact hole distortion is mainly caused by low mask selectivity, poor mask surface control (roughness, striation, pitting or pin hole) before and after etching. The surface roughness and mask selectivity have been studied to overcome the problem of pattern deformation of photoresist (PR) and C-rich materials as the mask. By using the polymer deposition process (PDP), the mask degradation is improved and the contact profile is well controlled. This paper focuses on the discussion of PDP chemistry selection, PDP time decision, and PDP used at before or after BARC (bottom anti-reflective coating) open step View full abstract»

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  • A Method of Manufacturing a Low Defect, Low Stress Pre-metal Dielectric Stack for High Reliability and MEMs Applications

    Publication Year: 2006 , Page(s): 88 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (577 KB) |  | HTML iconHTML  

    It is widely known in the semiconductor industry that CMP induced micro-scratches can cause not only an initial failure but also a long-term reliability problem. Silicon oxide films doped with boron and phosphorus have been standard in pre-metal dielectric stacks but are prone to CMP micro scratching. A novel film stack was developed utilizing a thick undoped PECVD cap layer to mitigate device failure and reliability problems. The sequence of depositing the integral film layers in conjunction with the densification proved critical in maintaining device performance View full abstract»

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  • Simulation and Design of an HDP-CVD Process for Planar Spacer Applications for Future DRAM Cell Concepts

    Publication Year: 2006 , Page(s): 93 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2326 KB) |  | HTML iconHTML  

    High density plasma chemical vapor deposition is a well known process for gap-fill applications. This paper describes the usage of high density plasma chemical vapor deposition to generate a buried isolation layer (planar spacer). A study to meet planar spacer requirements is presented based on simulations on reactor and feature scale. It explains variations from wafer center towards the edge in within-trench fill height uniformity, sidewall coverage and hat height. Plasma density variations across the wafer surface and subsequently deviations of incoming ions off the normal direction were found as the main contributor. Simulation results could be confirmed by several experiments. Based on these results a new type of high density plasma chemical vapor deposition process was designed to achieve homogenous within trench fill heights and pattern across the wafer and is therefore suitable for planar spacer applications View full abstract»

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  • Evaporation vs. Sputtering of metal layers on the Backside of Silicon wafers

    Publication Year: 2006 , Page(s): 99 - 103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    We present the results of the differences observed between evaporated and sputtered backside metallization processes on silicon wafers: these two methods of fabricating metal layers and the activation of the backside semiconductor-metal contact follow different physical mechanisms. Differing crystalline structures of the metal layers can be observed and the thermal budget of the overall process of the wafer is affected in different ways. In this paper, we describe these differences, provide a description of the known physical and mechanical mechanisms and propose some models. Additionally, we report a few production issues and experiences View full abstract»

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  • Application of Back-side Alignment of Thick Layers for the Manufacturing of Advanced Power Devices

    Publication Year: 2006 , Page(s): 104 - 107
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    Back-side alignment was implemented in the thick layer process flow for the production of advanced power devices. The alignment and overlay performance of the back-side alignment scheme are addressed, as well as the benefits in terms of productivity and cost reduction View full abstract»

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  • Low-K and Interconnect Stacks -- a Status Report

    Publication Year: 2006 , Page(s): 108 - 113
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9243 KB) |  | HTML iconHTML  

    One of the interesting aspects of the migration of low-k into state-of-the-art processes is that almost every manufacturer does it differently - as a generality, there seems to be a greater variety in the detail of low-k implementation than there was in the metal-dielectric structures in the "good old days" of aluminium metallization. Some manufacturers use a simple two-layer dielectric, dual-damascene matrix in their interconnect stack, and others have complex multilayers with single-damascene metal tracks and vias. Chipworks, as a supplier of competitive intelligence to the semiconductor and electronics industries, monitors the evolution of chip processes as they come into commercial production. Chipworks has obtained parts from leading edge manufacturers, and performed structural analyses to examine the features and manufacturing processes of the devices. The paper discusses how low-k dielectrics have been used by various vendors, and gives a comparison of their different back-end-of-line technologies. The paper will detail the physical structures we have analyzed, and also examine the different approaches to the use of low-k dielectric materials View full abstract»

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