Eleventh IEEE European Test Symposium (ETS'06)

21-24 May 2006

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  • Eleventh IEEE European Test Symposium

    Publication Year: 2006, Page(s): c1
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  • Eleventh IEEE European Test Symposium - Title

    Publication Year: 2006, Page(s):i - iii
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  • Eleventh IEEE European Test Symposium - Copyright

    Publication Year: 2006, Page(s): iv
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  • Eleventh IEEE European Test Symposium - TOC

    Publication Year: 2006, Page(s):v - viii
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  • Foreward

    Publication Year: 2006, Page(s): ix
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  • Organizing Committee

    Publication Year: 2006, Page(s):x - xi
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  • Steering and Program Committees

    Publication Year: 2006, Page(s): xii
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  • Test Technology Technical Council

    Publication Year: 2006, Page(s):xiii - xv
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  • Innovation and Wealth Creation from Technology

    Publication Year: 2006, Page(s): 3
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  • Living with Failure: Lessons from Nature?

    Publication Year: 2006, Page(s):4 - 8
    Cited by:  Papers (20)
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  • Low Cost Launch-on-Shift Delay Test with Slow Scan Enable

    Publication Year: 2006, Page(s):9 - 14
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (293 KB) | HTML iconHTML

    Most scan based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but require a fast scan enable. We present a low cost solution for implementing LOS tests by adding a small amou... View full abstract»

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  • Dynamic Voltage Scaling Aware Delay Fault Testing

    Publication Year: 2006, Page(s):15 - 20
    Cited by:  Papers (11)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (340 KB) | HTML iconHTML

    The application of dynamic voltage scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This... View full abstract»

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  • Enhancing Delay Fault Coverage through Low Power Segmented Scan

    Publication Year: 2006, Page(s):21 - 28
    Cited by:  Papers (19)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (204 KB) | HTML iconHTML

    Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan (Whetsel, 2000) and (Lee et al., 2004) has been shown to be an effective technique in addressing test power issues in industrial designs (Saxena et al., 2001). To achieve hig... View full abstract»

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  • Single-Event Upset Analysis and Protection in High Speed Circuits

    Publication Year: 2006, Page(s):29 - 34
    Cited by:  Papers (6)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (261 KB) | HTML iconHTML

    The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a no... View full abstract»

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  • Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study

    Publication Year: 2006, Page(s):35 - 42
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Smaller feature sizes and lower supply voltages make DSM devices more susceptible to soft errors generated by alpha particles and neutrons as well as other sources of environmental noise. In this scenario, soft-error/noise tolerant techniques are necessary for maintaining the SNR of critical DSP applications. This paper studies linear DSP circuits and discusses two low cost techniques for improvin... View full abstract»

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  • Minimal March Tests for Dynamic Faults in Random Access Memories

    Publication Year: 2006, Page(s):43 - 48
    Cited by:  Papers (9)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (196 KB) | HTML iconHTML

    The class of dynamic faults has been recently shown to be an important class of faults for the new technologies of random access memories (RAM) with significant impact on DPM levels. Very little research has been done in the design of memory test algorithms targeting dynamic faults. Two March test algorithms of complexity 11N and 22N, N is the number of memory cells, for subclasses of two-operatio... View full abstract»

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  • A 22n March Test for Realistic Static Linked Faults in SRAMs

    Publication Year: 2006, Page(s):49 - 54
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    Linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design a very complex task. Although several March tests have been developed for the wide memory faults spread, a few of them are able to detect linked faults. In the present paper March AB, a March test targ... View full abstract»

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  • Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories

    Publication Year: 2006, Page(s):55 - 62
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (211 KB) | HTML iconHTML

    With the shrinking feature size and the growing density, testing neighborhood pattern-sensitive faults (NPSFs) of integrated circuits is more and more important, especially testing NPSFs of semiconductor memories. This paper presents a test algorithm for detecting the active NPSFs (ANPSFs) in ternary content addressable memories (TCAMs). Due to the special TCAM cell structure, unique test algorith... View full abstract»

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  • Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics

    Publication Year: 2006, Page(s):63 - 68
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (294 KB) | HTML iconHTML

    Online repair through reconfiguration is a particularly advantageous approach in the nanoelectronic environment since reconfigurability is naturally supported by the devices. However, precise identification of faulty locations is of critical importance for fine-grain repairs. A CLA is mainly composed of: (1) carry generation blocks; and (2) g,p signal generation blocks. In this paper we propose tw... View full abstract»

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  • Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices

    Publication Year: 2006, Page(s):69 - 74
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1574 KB) | HTML iconHTML

    This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test executi... View full abstract»

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  • Fault Injection-based Reliability Evaluation of SoPCs

    Publication Year: 2006, Page(s):75 - 82
    Cited by:  Papers (12)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    Systems-on-programmable-chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming very attractive for safety-critical applications. However, the issue of assessing the reliability they can provide and debugging the possible saf... View full abstract»

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  • Retention-Aware Test Scheduling for BISTed Embedded SRAMs

    Publication Year: 2006, Page(s):83 - 88
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    In this paper we address the test scheduling problem for built-in self-tested (BISTed) embedded SRAMs (e-SRAMs) when data retention faults (DRFs) are considered. The proposed test scheduling algorithm utilizes the "retention-aware" test power model (Wang et al., 2005) to minimize the total testing time of e-SRAMs while not violating given power constraints. Without losing generality, we consider b... View full abstract»

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  • A Transparent based Programmable Memory BIST

    Publication Year: 2006, Page(s):89 - 96
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    We present an original transparent-based programmable memory BIST solution suitable for offline as well as online memory testing. Thanks to an appropriate combination of the test algorithm with the data backgrounds and by providing unlimited background flexibility, the proposed solution allows covering almost all existing fault models while increases the probability to also detect un-modeled fault... View full abstract»

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  • A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare

    Publication Year: 2006, Page(s):97 - 102
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    The increasing bandwidth requirements of mainstream computing and consumer products, as well as the inefficiency of embedded clock interfaces in terms of latency, protocol overhead and power requirements have caused the traditional source synchronous interfaces like DRAM memory to break the gigabit range. Above 1Gbps dynamic effects like drift and jitter might become critical for traditional test ... View full abstract»

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  • On-Chip Time Measurement Architecture with Femtosecond Timing Resolution

    Publication Year: 2006, Page(s):103 - 110
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    This paper presents a new on-chip time measurement architecture which is based on the time-to-digital conversion (TDC) method that is capable of achieving a timing resolution of tens of femtoseconds without the use of external automatic test equipment (ATE). This is the highest temporal resolution that has been reported to-date and is achieved by the use of the homodyne technique. The proposed arc... View full abstract»

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