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12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)

Date 13-15 March 2006

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  • Proceedings. 12th IEEE International Symposium on Asynchronous Circuits and Systems

    Publication Year: 2006, Page(s):c1 - c11
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  • 12th IEEE International Symposium on Asynchronous Circuits and Systems - Title Page

    Publication Year: 2006, Page(s):i - iii
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  • 12th IEEE International Symposium on Asynchronous Circuits and Systems - Copyright

    Publication Year: 2006, Page(s):iv - ivv
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  • 12th IEEE International Symposium on Asynchronous Circuits and Systems - Table of contents

    Publication Year: 2006, Page(s):v - vii
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  • Message from the Chairs

    Publication Year: 2006, Page(s):viii - viiii
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  • Committees

    Publication Year: 2006, Page(s): x
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  • Asynchronous design: an enabler for flexible microelectronics

    Publication Year: 2006, Page(s):1 pp. - xiii
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB) | HTML iconHTML

    Summary form only given. Flexible microelectronics technology featuring low-temperature polysilicon (LTPS) TFT and surface free technology by laser annealing and ablation (SUFTLAR) is expected to become a platform for developing thin, flexible and low-cost display devices. LTPS TFTs are good for realizing large area displays and integrated circuits at lower cost. A drawback of LTPS TFTs, however, ... View full abstract»

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  • Measuring deep metastability

    Publication Year: 2006, Page(s):10 pp. - 11
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB) | HTML iconHTML

    Present measurement techniques do not allow synchronizer reliability to be measured in the region of most interest, that is, beyond the first half cycle of the synchronizer clock. We describe methods of extending the measurement range, in which the number of metastable events generated is increased by four orders of magnitude, and events with long metastable times are selected from the large numbe... View full abstract»

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  • A level-crossing flash asynchronous analog-to-digital converter

    Publication Year: 2006, Page(s):11 pp. - 22
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB) | HTML iconHTML

    Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-to-digital converter (ADC) to process analog signals from the physical world. We describe a new topology for an asynchronous analog-to-digital converter, dubbed LCF-ADC, that has several major advantages over previously-d... View full abstract»

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  • An asynchronous high-throughput control circuit for proximity communication

    Publication Year: 2006, Page(s):9 pp. - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (353 KB) | HTML iconHTML

    We describe an asynchronous control circuit for interchip communication that enables high throughput proximity communication. The circuit has been fabricated in TSMC 180nm technology and operates over a wide range of coupling capacitances between the chips and over a wide range of supply voltages. At the nominal voltage of 1.8 V and a coupling capacitance of 40fF, this control circuit enables a th... View full abstract»

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  • Self-healing asynchronous arrays

    Publication Year: 2006, Page(s):12 pp. - 45
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (395 KB) | HTML iconHTML

    This paper presents a systematic method for designing of a self-healing asynchronous array in the presence of errors. By adding spare resources in one of three different ways and forcing the asynchronous circuit to stall in case of failure, the specific self-reconfiguration logic is activated by a deadlock detector and the array circuit can be reconfigured around the faulty components and recover ... View full abstract»

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  • Low-overhead testing of delay faults in high-speed asynchronous pipelines

    Publication Year: 2006, Page(s):11 pp. - 56
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (365 KB) | HTML iconHTML

    We propose a low-overhead method for delay fault testing in high-speed asynchronous pipelines. The key features of our work are: (i) testing strategies can be administered using low-speed testing equipment; (ii) testing is minimally-intrusive, i.e. very little testing hardware needs to be added; (iii) testing methods are extended to pipelines with forks and joins, which is an important first step ... View full abstract»

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  • A transistor-level test strategy for C/sup 2/MOS MOUSETRAP asynchronous pipelines

    Publication Year: 2006, Page(s):10 pp. - 67
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    We discuss a transistor-level test methodology for C2MOS asynchronous pipelines. Unlike their static CMOS counterparts, wherein testing for stuck-at faults and compliance to a few timing constraints typically suffices, dynamic asynchronous pipelines present new challenges which require more elaborate test solutions. More specifically, many gate-level input/output stuck-at faults of a st... View full abstract»

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  • A novel design method for asynchronous bundled-data transfer circuits considering characteristics of delay variations

    Publication Year: 2006, Page(s):10 pp. - 77
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    As the VLSI technology advances, delay variations become extremely large. Delay variation properties caused by various variation factors are different. However, the characteristics of delay variations have not been considered in traditional delay models or asynchronous design styles, which have, therefore, suffered large performance overhead. In this paper, we propose the following two methods for... View full abstract»

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  • An ultra-low energy asynchronous processor for wireless sensor networks

    Publication Year: 2006, Page(s):8 pp. - 85
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB) | HTML iconHTML

    This paper describes the design flow used for an asynchronous 8-bit processor implementing the Atmel AVR instruction set architecture. The goal is to show dramatic reductions in power and energy with respect to the synchronous case, while retaining essentially a traditional design flow. The processor was implemented in a 130nm technology using desynchronization, starting from an initial design dow... View full abstract»

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  • AsyncRFID: fully asynchronous contactless systems, providing high data rates, low power and dynamic adaptation

    Publication Year: 2006, Page(s):10 pp. - 97
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1505 KB) | HTML iconHTML

    This paper describes an original solution for improving inductive contactless telemetry powered devices. Rather than implementing asynchronous logic to provide digital circuit performance, we propose to apply the asynchronous logic paradigm to the whole system, providing high data rates, low power consumption on tags and dynamic performance adaptation. This flexibility allows a dynamic compromise ... View full abstract»

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  • ATRS: an alternative roadmap for semiconductors, technology evolution and impacts on system architecture

    Publication Year: 2006, Page(s):1 pp. - xiiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB)

    Summary form only given. The recent evolution of semiconductor technology, in the last decades, brought tremendous improvements in performance increase at decreasing prices, perfectly following the famous Moore's law. Lithography is still improving and allows 0.7times linear shrink per technology node. However, many products are hitting the "power wall"! Silicon is free, but peak power consumption... View full abstract»

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  • Surfing interconnect

    Publication Year: 2006, Page(s):9 pp. - 106
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    We present a novel approach to long-wire signalling. We use the traditional division of long wires into buffered segments, but the delay of each buffer is modulated by signals derived from a timing chain. This creates a circuit element whose timing behaviour is between that of an inverter and that of a latch. We call these "soft latches". We demonstrate the advantages of our approach by comparing ... View full abstract»

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  • Multiple-rail phase-encoding for NoC

    Publication Year: 2006, Page(s):10 pp. - 116
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (587 KB) | HTML iconHTML

    A novel self-timed communication protocol is based upon phase-modulation of a reference signal. The reference and the data are sent on the same transmission lines and the data can be recovered observing the sequence of events on the same lines. Employing several lines increases the number of states hence reducing the number of symbols required for a transmission. A new encoding algorithm is descri... View full abstract»

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  • Fast asynchronous shift register for bit-serial communication

    Publication Year: 2006, Page(s):10 pp. - 127
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    A fast asynchronous shift register is used as the serializer and deserializer in a novel bit-serial on-chip communication link. The link employs two-phase transition-based LEDR encoding. Acknowledgement is generated only at the word level, rather than bit by bit. The shift register is designed to achieve bit time of a single gate delay. It is based on a wave-pipelined control path and on transitio... View full abstract»

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  • Optimal technology mapping and cell merger for asynchronous threshold networks

    Publication Year: 2006, Page(s):10 pp. - 137
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    A key challenge in using robust asynchronous circuit styles is the lack of powerful automated optimization techniques. In this paper, optimal technology mapping and cell merger algorithms for robust asynchronous threshold networks are introduced. The technology mapping algorithm is the first systematically to target either delay or area, without destroying the hazard-freedom properties of the init... View full abstract»

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  • Synthesising heterogeneously encoded systems

    Publication Year: 2006, Page(s):11 pp. - 149
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    Self-timed datapaths require their data to be encoded in a delay-insensitive manner. The dual-rail encoding is commonly used, but more complex codes offer the possibility of better energy efficiency or fewer wires-per-bit. However, these advantages are often negated by datapath manipulations within large systems that require code-groups to be split and reformed. These overheads may be reduced by h... View full abstract»

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  • Asynchronous architectures for nanometer scales

    Publication Year: 2006, Page(s):1 pp. - xivv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (22 KB)

    Summary form only given. The ongoing developments in nanotechnology promise extremely powerful computers, but they may require new designs. Heat dissipation will become a major issue at the high integration densities allowed by nanotechnology, and it is therefore unsurprising that techniques to reduce it, like asynchronous timing, have attracted growing interest in recent years. At the same time, ... View full abstract»

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  • GALS at ETH Zurich: success or failure?

    Publication Year: 2006, Page(s):10 pp. - 159
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1411 KB) | HTML iconHTML

    The Integrated Systems Laboratory (IIS) of ETH Zurich (Swiss Federal Institute of Technology) has been active in globally-asynchronous locally-synchronous (GALS) research since 1998. During this time, a number of GALS circuits have been fabricated and tested successfully on silicon. From a hardware designers point of view, this article summarizes the evolution from proof of concept designs over mu... View full abstract»

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  • Interface design for rationally clocked GALS systems

    Publication Year: 2006, Page(s):12 pp. - 171
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    We investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delay-augmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of... View full abstract»

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