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Circuits and Devices Magazine, IEEE

Issue 6 • Date Nov. 1987

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  • Front cover

    Publication Year: 1987 , Page(s): c1
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  • [Inside front cover]

    Publication Year: 1987 , Page(s): c2
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  • Contents

    Publication Year: 1987 , Page(s): 1
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  • List of staffs

    Publication Year: 1987 , Page(s): 2
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  • More on SOI

    Publication Year: 1987 , Page(s): 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (303 KB)  

    This is the second of two issues on the subject of silicon-on-insulator (SOI) devices. Our collection of articles includes a third material technique (oxidation of porous silicon), design considerations for SOI, and some potential and existing applications. A total of 12 articles from four countries make up these two issues, and we received some 23 responses advertising activity in the SOI area. I would like to express my appreciation to each of these authors for their contributions, which have provided us with an excellent perspective on SOI materials and devices. View full abstract»

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  • Porous silicon techniques for SOI structures

    Publication Year: 1987 , Page(s): 3 - 7
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3165 KB)  

    Among the most promising techniques for producing silicon-on-insu-lator (SOI) substrates suitable for fabrication of high-performance devices are those based on the oxidation of porous silicon. Porous silicon has a unique set of material properties, which lends itself to a variety of different SOI fabrication techniques. View full abstract»

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  • Considerations for the design of an SRAM with SOI technology

    Publication Year: 1987 , Page(s): 8 - 10
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1705 KB)  

    Several exciting circuit opportunities are available as a result of recent advances in silicon-on-insulator (SOI) material. These include radiation-hardened memories for space applications, bipolar SOI, the combination of bipolar and CMOS on the same chip, and three-dimensional integration. With all these advances, the first significant application of SOI in operational systems appears most likely to be an SRAM using CMOS circuitry, designed for space applications. The requirements for a space-based memory are well matched to properties that can be provided by CMOS devices fabricated on SOI material. These requirements include hardness to gamma radiation (total-dose hardness) and resistance to upset from ionizing particles (SEU), in addition to the more usual requirements of high density, high speed, low power, and high reliability. View full abstract»

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  • SOI technology using buried layers of oxidized porous Si

    Publication Year: 1987 , Page(s): 11 - 15
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4784 KB)  

    Porous silicon was formed in the highly doped layers of an n/n+/n structure. After full oxidation of porous silicon, CMOS devices were fabricated in insulated single-crystal silicon islands. Mobilities comparable to bulk silicon are measured, and low-leakage junctions are realized. View full abstract»

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  • Some properties of thin-film SOI MOSFETs

    Publication Year: 1987 , Page(s): 16 - 20
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    This paper describes the properties that can be expected from thin-film SOI-MOS transistors. Simple qualitative modeling shows that improvements of different parameters, such as subthreshold slope, hot-electron effects, and short-channel effects, can be obtained when thin, fully depleted films are used. View full abstract»

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  • Total-dose effects of gamma-ray irradiation on CMOS/SIMOX devices

    Publication Year: 1987 , Page(s): 21 - 26
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6958 KB)  

    Radiation-hardened CMOS/SIMOX devices have been developed using a combination of vertical isolation structures obtained by SIMOX technology and newly developed lateral isolation structures. The n-channel MOSFET is vertically isolated by multilayers of highly oxygen-doped polysilicon and buried SiO2, and is laterally isolated by multilayers of thin sidewall SiO2, sidewall polysilicon, and thick field SiO2. The p-channel MOSFET has the same vertical isolation structure as that of the n-channel MOSFET. However, it has no sidewall polysilicon layer but uses a thick field SiO2 layer for lateral isolation. Highly oxygen-doped polysilicon and sidewall polysilicon layers act to shield radiation-induced positive charges trapped in the buried SiO2 and field SiO2 layers, respectively. By utilizing these isolation structures and a thin-gate SiO2 layer, the developed CMOS/SIMOX devices exhibited ample operational characteristics even after exposure to 2 Mrad(Si) of 60Co gamma-ray irradiation. View full abstract»

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  • Bidirectional blocking junctions in SOI

    Publication Year: 1987 , Page(s): 27 - 30
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4028 KB)  

    Back-to-back junction (n-p-n) structures were fabricated in silicon-on-sapphire (SOS), in polysilicon-on-SiO2, and in silicon-on-insulator (SOI) prepared by high-dose oxygen ion implantation. Since the structure is actually a bipolar transistor operated with an open base, the geometry and doping levels were adjusted to spoil its gain and thereby achieve symmetrical bidirectional blocking. In all three cases, ideal plane-junction breakdown was observed for both polarities of applied voltage when precautions were taken to avoid local field-enhancing geometries. View full abstract»

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  • Purposes of three-dimensional circuits

    Publication Year: 1987 , Page(s): 31 - 33
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2849 KB)  

    Three-dimensional (3-D) circuitry is a recognized concept. With the advent of silicon-on-insulator (SOI) technologies, this idea is being realized using techniques such as laser recrystallization of polysilicon, which allows fabrication of active devices stacked in two or more layers. Since silicon is a well-known microelectronic material, progress has been very fast and some laboratories have already succeeded in producing three-dimensional circuit cells [1]-[3]. In order to focus activity and rationally optimize products, technologists need to know the types of circuits required. This paper examines the problem from several points of view and tries to answer three fundamental questions: (1) What are the main advantages of 3-D circuitry? (2) What kind of circuits will yield best advantages? (3) Which technological problems have priority? View full abstract»

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  • Circuit simulation and modeling

    Publication Year: 1987 , Page(s): 34 - 38
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  • The PC in electrical engineering

    Publication Year: 1987 , Page(s): 38 - 42
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  • EDS column

    Publication Year: 1987 , Page(s): 42 - 44
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  • LEOS column

    Publication Year: 1987 , Page(s): 44 - 45
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  • Call for papers

    Publication Year: 1987 , Page(s): 46
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  • Executive column

    Publication Year: 1987 , Page(s): 47 - 49
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  • Book reviews

    Publication Year: 1987 , Page(s): 49 - 53
    Cited by:  Papers (1)
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  • News and events

    Publication Year: 1987 , Page(s): 54
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  • CAS column

    Publication Year: 1987 , Page(s): 54 - 57
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  • Conference calendar

    Publication Year: 1987 , Page(s): 58
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  • Call for papers

    Publication Year: 1987 , Page(s): 1
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  • Announcement

    Publication Year: 1987 , Page(s): 60
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  • Author index

    Publication Year: 1987 , Page(s): 61 - 64
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Aims & Scope

IEEE Circuits and Devices Magazine (1985-2006) covers the design, implementation, packaging, and manufacture of micro-electronic and photonic devices, circuits and systems

 

This Magazine ceased publication in 2006.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dr. Ronald W. Waynant
r.waynant@ieee.org