SNDR sensitivity analysis for cascaded /spl Sigma//spl Delta/ modulators

Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded /spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.