A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM

A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.