Bus buffer modeling and optimization in video processing IP

One important issue for IP-based (Intellectual Property) design is the bus and memory bandwidth budget for a set of IP cores and customized functional units plugging into on-chip bus. In this paper, we propose the bus buffer modeling and the buffer optimization procedure to make the buffer an analytical design. Due to applicability for IP integration, the proposed model has the features of parametrics and generality and is not restricted to some specific process rate or bus transactions. Also the optimization procedure is deterministic, not determined by real-case simulation. With the help of the proposed bus buffer generation algorithm, bus buffer attributes can be determined for implementation.