Video scaling processor targeted for low-power applications

Article presents the concept of a smart video scaling method and its low-power hardware implementation. The proposed algorithm has been developed as the result of analysis of several fundamental methods. Different scaling approaches were investigated with respect to the computational complexity and perceived video quality. Proposed algorithm is a mixed solution. When high-quality video is required then two-dimensional polyphase filtering interpolation is applied, whereas nearest neighbor method can be enabled for low-complexity processing mode. This hybrid approach is applied in the presented video scaling processor, which supports up and down-scaling of input video frames up to 8K pixels of resolution. Scaling ratio is arbitrary for both horizontal and vertical direction. Thanks to advanced architecture-level and register-level clock gating, as well as an implemented power save mode, the dynamic power consumption in the design is significantly reduced. The paper is summarized with the design synthesis results under FPGA and ASIC technology. Obtained parameters are also compared with several competitive scaling solutions.