Technology migration of analogue CMOS circuits using hooke-jeeves algorithm and genetic algorithms in multi-core CPU systems

In this paper a new approach for technology migration of analogue CMOS circuits is presented. The Hooke-Jeeves algorithm and genetic algorithms, are considered for multi criteria optimization in conjunction with HSPICE simulation software. Their goal is to calculate the values for circuits' elements for implementation in certain technology of fabrication. The modifications and improvements introduced in generic Hooke-Jeeves algorithm for multi-core CPUs are described. The methodology of migration is presented and verified with a several circuit examples passed between TSMC 0.18 μm and TSMC 90 nm CMOS fabrication processes. The paper is concluded by comparing the migration speed and reliability for the two implemented migration strategies.