Design of a SOI memory cell

In this paper a quantitative analysis has been used for describing and discussing design characterizations of an SOI flash memory cell. Mathematical expressions for the front gate threshold voltage of the SOI memory cell are derived using the equations for a standard SOI MOSFET. Coupling coefficients which exist between the control gate and source and drain regions, are the same as for the silicon body, through stored charge at the floating gate has to be included in these equations and the mathematical expressions for the flash memory cell can be obtained. Implementing this, the voltage of the front gate of a standard SOI MOSFET is equal to the voltage of the floating gate of the memory cell. During analysis, the emphasis is put on the case where the back channel is depleted, because then coupling between the front and back gate can control the threshold voltage of the control gate.