A field-plated drift-length scalable EDPMOS device structure

This paper presents a new field-plated p-channel extended drain (FP EDPMOS) device in which the drain is depleted by the combination of a surface field plate and buried silicon junction(s). The breakdown voltage is layout scalable from 35V to over 80V, achieving a best-in-class R
sp
-BV
ds
figure-of-merit of 1.10 mOhm cm
²
for 70V BV
ds
. Super-linear output characteristics and full forward safe operating characteristics result in a power RF figure-of-merit of at least 700 GHzV and 525 GHzV for 45V/75V device-ratings, respectively. This FP EDPMOS device construction is ideally suited for integrated power switching applications and low-cost RF power amplification modules.