Effect of device layout on the thermal resistance of high-power thermally-shunted heterojunction bipolar transistors

The effect of device layout on thermal impedance of thermally-shunted HBTs was investigated. A direct comparison of thermally shunted devices and standard airbridge devices is made. Changes in thermal resistance of up to 67% were observed. While thermal resistance remains sensitive to emitter element placement in thermally shunted devices, variations in the location of thermal shunt landings had little effect. These results provide a basis for optimizing thermally-shunted devices.