ISPSD `07 Best Paper Award; Record-Low On-Resistance for 0.35 μm based Integrated XTREMOSTM Transistors

Experimental data are shown for integrated smart power transistors breaking the silicon limit at 100V. The performance is close to the much lower super-junction limit for the given device pitch. The device uses standard trench technology and is implemented in a 0.35 μm smart power process. Key steps to improve device performance yielding a record performance of 30 mOhm*mm
²
for a V
_bd
of 94V are highlighted in the paper.