High microwave power InP MISFETs with one micron and submicron gates

High-power microwave InP MISFETs were investigated. The gate insulator in the InP MISFET was silicon dioxide (SiO/sub 2/) with a thin (<50 AA) silicon interfacial layer (SIL) deposited by direct plasma-enhanced chemical vapor deposition (PECVD). MIS capacitors were formed on n-type InP using the SiO/sub 2/ and the SiO/sub 2//Si gate insulators. A 1.2 V hysteresis was present in the capacitance-voltage (C-V) curve of the capacitors with SiO/sub 2/, but essentially no hysteresis was observed in the C-V curve of the capacitors with SIL incorporated in the insulator. InP power MISFETs with the SIL exhibited excellent stability with drain current drift of less than 3% in 10/sup 4/ s as compared to 15-18% drift in 10/sup 4/ s for MISFETs without SIL. MISFETs with SIL in the gate insulator had an output power density of 1.75 W/mm at 9.7 GHz with 24% power-added efficiency and an associated power gain of 2.5 dB.<
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