Characterization of back-channel subthreshold conduction of walled SOI devices

Submicrometer CMOS transistors with junctions walled to a trenched isolation oxide have been fabricated on SIMOX substrates. Back-channel leakage of the devices was measured as a function of substrate bias. Compared with nonwalled devices, walled devices showed early turn-on of the back-channel at relatively low substrate biases. This phenomenon is caused by the two-dimensional electrical field effect at the bottom corner of the device sidewalls, and is supported by PISCES simulation.