On the optimum 2/sup nd/ harmonic source and load impedances for the efficiency-linearity trade-off of RF LDMOS power amplifiers

For the first time, a systematic analysis of the simultaneous impact of the second harmonic source and load terminations on the linearity-efficiency trade-off of LDMOS power amplifiers (PAs) is presented. For the combinations studied, it can be concluded that, contrary to common design practice, open-circuiting both the input and output of an RF LDMOS PA at the second harmonic frequency results in the best trade-off. On-wafer large-signal measurements with the above-mentioned optimal impedances have been carried out with single carrier IS-95 CDMA and 3GPP-WCDMA signals at 2.14 GHz. The device used contains a total gate width of 2 mm. For the IS-95 CDMA signal, an output power (P/sub out/) of 223 mW/mm, and a power-added efficiency (PAE) of 35% are obtained at -45 dBc ACPR. This obtained P/sub out/ corresponds to only 3.0 dB of back-off. For the 3GPP-WCDMA signal, the -45 dBc ACPR specification at 5 MHz offset is satisfied at 6 dB in back-off with P/sub out/=126 mW/mm, and 33% PAE.