A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS

This paper describes a 25 GHz clock buffer and 50 Gb/s 2-to-1 selector, which are implemented in 90 nm CMOS using 48 nm transistors, and operate off a 1 V supply. An inductor-peaked CMOS inverter is employed for the clock buffer. The selector is equipped with a tail transistor whose gate is switched by the rail-to-rail clock signal produced by the buffer.