An instruction set for the efficient implementation of the CORDIC algorithm

In this paper, an instruction set for a processor is proposed which is very well suited for the implementation of the CORDIC algorithm. This instruction set is efficient for both the hardware implementation of the processor and the CORDIC software implementation. This is achieved by conditional instructions which reduce the number of lines of code significantly. In order to implement the conditional instructions in the processor hardware model with a conventional ALU, only a few additional gates are necessary. Thus, the increase in area and timing of the processor is negligible due to these additional instructions. The presented approach is a very good trade-off from a hardware/software co-design perspective if both the hardware and software efficiency is important.