Cost Comparison of FO‐WLP with Other Technologies

This chapter analyzes the cost of fan‐out wafer‐level packaging (FO‐WLP). It discusses the cost of FO‐WLP itself and includes comparisons between FO‐WLP and other technologies. All cost comparisons in this chapter are carried out using activity‐based cost modeling. With activity‐based cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is calculated. The comparisons in this chapter focus on the direct costs for each technology, although factories for flip chip and wire bond assembly, substrate fabrication, and fan‐out packaging will have different overhead and indirect cost considerations. The package‐on‐package (PoP) process is also described. Newer versions of PoP such as FO‐WLP may be cost‐effective, even compared to PoP designs that use more mature technology, if the number of necessary routing layers can be reduced.