Clock and Timing in Wireline Communications

The chapter reviews the basics of timing and clock and data recovery circuits in high speed links, inluding system level considerations, limitations of the linear model, pull-in process and false lock, and a case for and key features of time domain event-driven system model to capture the effect of the circuit parameters on system performance. The second part of the presentation reviews the circuits for phase detection and modeling of samplers for fast and accurate system level modeling.