Circuit Errors in Switched‐capacitor ΣΔ Modulators

This chapter analyzes the main nonideal mechanisms affecting the performance of switched‐capacitor (SC) ΣΔMs. It analyses the circuit errors with a large influence on the behavior of SC‐ΣΔMs ‐ such as integrator leakage, capacitor mismatch, settling errors, and kT/C noise. The chapter establishes system‐level considerations, behavioral models, and closed‐form expressions for the influence of each nonideality. The way in which these nonidealities affect the performance of ΣΔMs depends on many different factors: the nature of the error itself, the influence of the specific circuit, its effect on the modulator noise transfer function, and so on. Speed limitations in SC integrators due to the limited dynamic response of amplifiers cause errors in the charge transfer. SC‐ΣΔMs are affected in practice by timing uncertainties in the clock phases that control the SC operation. The effect of clock jitter in SC‐ΣΔMs is mainly limited to a sampling uncertainty of the modulator input signal.