Taxonomy of ΣΔ Architectures

This chapter presents an overview of practical topologies for the implementation of ΣΔ modulation. It focuses on the second‐order ΣΔ modulator and the cascade ΣΔ topologies. It considers higher‐order single‐loop ΣΔ architectures, taking into account issues related to their practical implementation and problems not addressed by linear models, such as instabilities. The topological study is extended to ΣΔ modulators using multi‐bit embedded quantizers, analyzing their pros and cons. The chapter covers conversion of band‐pass signals, taking into account its application in wireless receivers. It deals with the main synthesis methods for designing continuous time (CT)‐ ΣΔ modulators, based on a discrete‐to‐continuous time (DT‐CT) transformation or a direct synthesis of the CT‐ ΣΔ modulator loop filter. The chapter addresses the realization of CT ΣΔ modulators, discussing their advantages compared to DT ones and the existing alternatives for the loop filter and the feedback implementation.