Understanding Shared‐Bus and Shared‐Memory Switch Fabrics

This chapter discusses the most common switch fabrics used in switch/router and router architectures. There are many different methods and trade‐offs involved in implementing a switch fabric and its associated queuing mechanisms, and each approach has very different implications for the overall design. The chapter discusses three main types of data blocking in switch fabric: internal blocking, output blocking and Head‐of‐Line (HOL) blocking. It shows a high‐level view of hierarchical bus architecture and high‐level architectures of the distributed output buffered switch. In a hierarchical bus architecture, the main backplane bus is typically configured to have usable bandwidth less than the aggregate bandwidth of all the ports in the system. The chapter also shows a high‐level architecture of a typical shared memory fabric. It summarizes the major electronic design problems encountered during the design of switch fabrics. The chapter also discusses the emerging requirements for high‐performance switch fabrics.