Delta‐Sigma DACs

This chapter discusses the specific issues involved in the design of delta‐sigma digital to analog converters (DACs). Qualitatively, the sensitivity considerations discussed for ADC loops remain valid for DAC loops, except that the errors generated here are due to coefficient truncations and to the round‐off errors of the digital operations, rather than element‐matching errors and finite opamp‐gain effects. Higher‐order error‐feedback loops can, of course, also readily be designed, subject to stability considerations. The motivation for paying such a high price for the one‐bit system was to avoid the inherent nonlinearities of a multi‐bit internal DAC. The input signal in this structure is converted by the 1‐bit DAC in a potentially linear fashion, while the M‐bit circuitry is used to cancel the large 1‐bit truncation error in the output, and replace it with a much smaller M‐bit error. The charges delivered by the unit element capacitors are adjusted sequentially, using a variable reference voltage for each element, until all charges match a fixed reference charge.