Discussion on Design Feasibility and Prospect of High‐Performance Sub‐50 nm Channel Single‐Gate SOI MOSFET Based on the ITRS Roadmap

The aggressive downscaling of metal oxide semiconductor field‐effect transistors (MOSFETs) continues unabated, leading to advanced applications that will support various social demands. This chapter presents an advanced design guideline for sub‐50 nm channel planar single‐gate (SG) SOI MOSFETs. It describes the lateral diffusion length of source and drain diffusion regions (Lld) because they play a significant role in suppressing the short‐channel effect. The chapter describes the 2‐D device simulator, Synopsys‐ Device Simulation for Smart Integrated Systems (DESSIS) with the hydrodynamic transport model. It shows how to design high‐performance sub‐50 nm channel SG SOI MOSFETs that have low‐standby power consumption. Intrinsic delay time and power‐delay product are examined on the basis of many simulation results. A comprehensive design guideline for scaled SG SOI MOSFETs was derived from the viewpoints of high‐speed operation and low power consumption or low standby power consumption.